Displaying 4 results from an estimated 4 matches for "svm_function_t".
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svm_function
2013 Apr 19
0
[PATCH] x86/HVM: move per-vendor function tables into .init.data
...;
}
-struct hvm_function_table * __init start_svm(void)
+const struct hvm_function_table * __init start_svm(void)
{
bool_t printed = 0;
@@ -1961,7 +1961,7 @@ static void svm_invlpg_intercept(unsigne
svm_asid_g_invlpg(curr, vaddr);
}
-static struct hvm_function_table __read_mostly svm_function_table = {
+static struct hvm_function_table __initdata svm_function_table = {
.name = "SVM",
.cpu_up_prepare = svm_cpu_up_prepare,
.cpu_dead = svm_cpu_dead,
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1504,7 +1504,7...
2012 Sep 11
0
[PATCH 1/3] x86/hvm: don't use indirect calls without need
...b/xen/arch/x86/hvm/svm/svm.c
@@ -73,6 +73,8 @@ bool_t cpu_has_lmsl;
#define set_segment_register(name, value) \
asm volatile ( "movw %%ax ,%%" STR(name) "" : : "a" (value) )
+static void svm_update_guest_efer(struct vcpu *);
+
static struct hvm_function_table svm_function_table;
/* va of hardware host save area */
@@ -269,9 +271,9 @@ static int svm_vmcb_restore(struct vcpu
v->arch.hvm_vcpu.guest_cr[2] = c->cr2;
v->arch.hvm_vcpu.guest_cr[3] = c->cr3;
v->arch.hvm_vcpu.guest_cr[4] = c->cr4;
- hvm_update_guest_cr(v, 0);
- hvm...
2012 May 30
12
[PATCH v2 0/4] XEN: fix vmx exception mistake
Changes from v1:
- Define new struct hvm_trap to represent information of trap, include
instruction length.
- Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of
wrappers around that function for existing callers, so that their parameter
lists actually *shrink*.
This series of patches fix the mistake for debug exception(#DB), overflow
exception(#OF) and INT3(#BP),
2012 Dec 10
26
[PATCH 00/11] Add virtual EPT support Xen.
From: Zhang Xiantao <xiantao.zhang@intel.com>
With virtual EPT support, L1 hyerpvisor can use EPT hardware
for L2 guest''s memory virtualization. In this way, L2 guest''s
performance can be improved sharply. According to our testing,
some benchmarks can show > 5x performance gain.
Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com>
Zhang Xiantao (11):