search for: suredp

...u show me what to look for in SM35 I can probably find it on my own for SM20/SM30/SM50. In case you're interested in looking at the mesa code, It's available on my atomic2 branch at: https://github.com/imirkin/mesa/commits/atomic2 . However I hardly expect you to debug my buggy code :) The SUREDP stuff is about surface RED ops, the existing code uses it but I'm going to leave it for image support and break direct buffer accesses directly into OP_ATOM (and in NVIDIA terminology RED is just ATOM without a destination). Thanks, -ilia On Fri, Oct 2, 2015 at 5:48 PM, Robert Morell <r...

Hello, I've recently come across an error reported by the GPU and would like to know what it means and especially what causes it to be triggered. Any information would be very useful: I'm seeing MP warp error 0x10 (appears in MP register 0x48). This is what we currently have in nouveau: <reg32 offset="0x048" name="TRAP_WARP_ERROR"> <!-- ctx-switched -->

...1, 1, // EMIT, RESTART 1, 1, 1, // TEX, TXB, TXL, - 1, 1, 1, 1, 1, 2, // TXF, TXQ, TXD, TXG, TEXCSAA, TEXPREP + 1, 1, 1, 1, 1, 1, 2, // TXF, TXQ, TXD, TXG, TXLQ, TEXCSAA, TEXPREP 1, 1, 2, 2, 2, 2, 2, // SULDB, SULDP, SUSTB, SUSTP, SUREDB, SUREDP, SULEA 3, 3, 3, 3, // SUBFM, SUCLAMP, SUEAU, MADSP 0, // TEXBAR @@ -57,7 +57,7 @@ const uint8_t Target::operationSrcNr[OP_LAST + 1] = 0 }; -const OpClass Target::operationClass[OP_LAST + 1] = +const OpClass Target::operationClass[] = { // NOP; PH...

...do some research and get back to you, hopefully within a few days. > In case you're interested in looking at the mesa code, It's available > on my atomic2 branch at: > https://github.com/imirkin/mesa/commits/atomic2 . However I hardly > expect you to debug my buggy code :) The SUREDP stuff is about surface > RED ops, the existing code uses it but I'm going to leave it for image > support and break direct buffer accesses directly into OP_ATOM (and in > NVIDIA terminology RED is just ATOM without a destination). Neat. I'll take a look at it. Thanks, Robert &g...