search for: superscalars

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might be a good start for > generic

From: Maciej ?enczykowski <maze at cela.pl> > That's a good point - does anyone know what the new Intel > Virtualization thingamajig in the new dual core pentium D's is about? It's all speculation at this point. But there are _several_ factors. But I'm sure the first time Intel saw AMD's x86-64/PAE52 presentation, the same thing popped into my mind that popped

Hi Phil. You more or less answered your own question, but let me give you some more info. Maybe it is of use. >From what I understand the SchedMachineModel is the future, although it is not as powerful as itineraries at present. The mi-scheduler is mostly developed around out-of-orders cores, I believe (I love to hear arguments on the contrary). Some of the constraints that can be found in

From: alex at milivojevic.org > At various points in time Red Hat made some somewhat conflicting > decisions. The first was that Red Hat distributions must have NPTL. > For NPTL support, there are two components of system where it is > implemented, kernel and glibc. Back then glibc supported NPTL only > for i686. NPTL support was later backported to i586 and i486. Also remember

Hi Sjoerd, On Fri, May 3, 2019 at 8:19 AM Sjoerd Meijer via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > I read that out-of-order cores are supported. How about in-order cores? > Would it be easy/difficult to add support for that? > > Cheers, > Sjoerd. > > I don't think that it would be difficult to support in-order superscalar cores. However, it would

Portable OpenCL (pocl) v0.6 released ------------------------------------ Portable OpenCL aims to be an efficient open source (MIT-licensed) implementation of the OpenCL 1.2 standard. In addition to producing an easily portable open source OpenCL implementation, another major goal of the project is improving performance portability of OpenCL programs with compiler optimizations, reducing the

On 19 Nov 2013, at 17:58, Kostya Serebryany <kcc at google.com> wrote: > On Tue, Nov 19, 2013 at 9:56 PM, Kuperstein, Michael M <michael.m.kuperstein at intel.com> wrote: >> What I’m trying to say is that according to my understanding of the C++11 memory model, even in that small reproducer, the store to g and the load from g are in fact a data race. >> >> (This

I've updated CentOS 4.0 to 4.1 on several machines (some desktops, some servers). However on my laptop, update is failing with following error just after headers are downloaded: --> Running transaction check --> Processing Dependency: glibc-common = 2.3.4-2 for package: glibc --> Finished Dependency Resolution Error: Missing Dependency: glibc-common = 2.3.4-2 is needed by package

On Tue, Nov 19, 2013 at 10:20 PM, David Chisnall < David.Chisnall at cl.cam.ac.uk> wrote: > On 19 Nov 2013, at 17:58, Kostya Serebryany <kcc at google.com> wrote: > > > On Tue, Nov 19, 2013 at 9:56 PM, Kuperstein, Michael M < > michael.m.kuperstein at intel.com> wrote: > >> What I’m trying to say is that according to my understanding of the > C++11

----- Original Message ----- > From: "Kostya Serebryany" <kcc at google.com> > To: "David Chisnall" <David.Chisnall at cl.cam.ac.uk> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Tuesday, November 19, 2013 11:01:12 PM > Subject: Re: [LLVMdev] Curiosity about transform changes under Sanitizers (Was: [PATCH]

I am currently looking at the Experimental MIPS backend and using it as a model. One thing I am currently however not sure about is instruction scheduling. Does LLVM have a pass which copes with instruction dependencies which will reorder instructions to minimize latencies (and given a model of the CPU try to find a good ordering for superscalar cpus? Is there an example of how this sort of thing

Portable OpenCL aims to be an efficient open source (MIT-licensed) implementation of the OpenCL 1.2 standard. In addition to producing an easily portable open source OpenCL implementation, another major goal of the project is improving performance portability of OpenCL programs with compiler optimizations, reducing the need for target-dependent manual optimizations. At the core of pocl is the

Portable Computing Language (pocl) v0.8 released Pocl's goal is to become an efficient open source (MIT-licensed) implementation of the OpenCL 1.2 (and soon OpenCL 2.0) standard. In addition to producing an easily portable open-source OpenCL implementation, another major goal of this project is improving performance portability of OpenCL programs with compiler optimizations, reducing the

The following is from Eric Raymond's new book on Unix programming. You'll get more insight from using profilers if you think of them less as ways to collect individual performance numbers, and more as ways to learn how performance varies as a function of interesting parameters ... Try fitting those numbers to a model, using open-source software like R or a good-quality

Hi Phil, > I've been watching this presentation from a 2014 LLVM dev meeting Thanks for your sharing! I am reviewing: * The chapter 10 (Instruction Level Parallelism) and chapter 11 (Optimizing for Parallelism and Locality) of Compiler Principle[1] * Adding and Optimizing a Subtarget for MIScheduler[2] by Dave Estes * Scheduler for in-order processors - what's present and

While I know that, technically, the only i586 machines are the Pentium and Pentium MMX, it is still nice that I can use some headless AMD K6/2 machines I have lying around for CentOS 4. Many thanks for the effort expended to get that working. -- Lamar Owen Director of Information Technology Pisgah Astronomical Research Institute 1 PARI Drive Rosman, NC 28772 (828)862-5554 www.pari.edu

Hi, On Fri, Jun 4, 2010 at 5:18 AM, Pekka Nikander <pekka.nikander at nomadiclab.com> wrote: >  Would the best way be to add an option to -loop-unroll, and hack away at lib/Transforms/Utils/LoopUnroll.cpp? Instead, the better alternative is to write another pass similar to LoopUnrollPass.cpp (say LoopPeelPass.cpp) and add new option -loop-peel. The new pass could use llvm::UnrollLoop()

Hi, On my x86_64 system I have a SiL311x controller that can do RAID. If I configure my 2 identical disks in a RAID1 setup, I would expect to see only 1 block device on Linux. Still I see 2 block devices. Is this intentional, and if so, isn't that dangerous ? (i.e. writing to both disks at the same time) Anyone with an insight, please explain :) -- dag wieers, dag at wieers.com,

On Nov 11, 2009, at 3:27 AM, Rodolph Perfetta wrote: > > If you know about the alignment, maybe use structured load/store > (vst1.64/vld1.64 {dn-dm}). You may also want to work on whole cache > lines > (64 bytes on A8). You can find more in this discussion: > http://groups.google.com/group/beagleboard/browse_thread/thread/12c7bd415fbc >

On Sep 17, 2013, at 11:04 AM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > 1. The SD schedulers significantly impact the spill counts and the execution times for many benchmarks, but the machine instruction (MI) scheduler in 3.3 has very limited impact on both spill counts and execution times. Is this because most of you work on MI did not make it into the 3.3 release?