Displaying 7 results from an estimated 7 matches for "superregisterclass".
2008 Oct 18
2
[LLVMdev] INSERT_SUBREG node.
...; >>
> > it is, though we have a workaround.
> >
> > We have 16-bit registers class and want to set both the lo and high
> > parts using INSERT_SUBREG.
> >
> > The workaround is to declare the same SubRegClass twice while
> > declaring
> > the SuperRegisterClass. i.e.
> >
> > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> > let SubRegClassList = [FSR8, FSR8]; // HERE.
> > }
>
> This is a bug, probably in tablegen. Unfortunately I don't have the
> time to fix it. But please file a bu...
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...ifying the sub-registers and making
> use of insert_subreg, no?
>
> Evan
>
it is, though we have a workaround.
We have 16-bit registers class and want to set both the lo and high
parts using INSERT_SUBREG.
The workaround is to declare the same SubRegClass twice while declaring
the SuperRegisterClass. i.e.
def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
let SubRegClassList = [FSR8, FSR8]; // HERE.
}
SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>;
SubRegSet : <2, [FSR0, FSR1], [FSR0H, FSR0L]>;
I think the fundamental problem we have there is that w...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
...; it is, though we have a workaround.
>>>
>>> We have 16-bit registers class and want to set both the lo and high
>>> parts using INSERT_SUBREG.
>>>
>>> The workaround is to declare the same SubRegClass twice while
>>> declaring
>>> the SuperRegisterClass. i.e.
>>>
>>> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
>>> let SubRegClassList = [FSR8, FSR8]; // HERE.
>>> }
>>
>> This is a bug, probably in tablegen. Unfortunately I don't have the
>> time to fix it....
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...insert_subreg, no?
>>
>> Evan
>>
> it is, though we have a workaround.
>
> We have 16-bit registers class and want to set both the lo and high
> parts using INSERT_SUBREG.
>
> The workaround is to declare the same SubRegClass twice while
> declaring
> the SuperRegisterClass. i.e.
>
> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> let SubRegClassList = [FSR8, FSR8]; // HERE.
> }
This is a bug, probably in tablegen. Unfortunately I don't have the
time to fix it. But please file a bug about this. Hopefully someone
w...
2008 Oct 20
2
[LLVMdev] INSERT_SUBREG node.
...> We have 16-bit registers class and want to set both the lo and
> > > > high
> > > > parts using INSERT_SUBREG.
> > > >
> > > > The workaround is to declare the same SubRegClass twice while
> > > > declaring
> > > > the SuperRegisterClass. i.e.
> > > >
> > > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> > > > let SubRegClassList = [FSR8, FSR8]; // HERE.
> > > > }
> > >
> > > This is a bug, probably in tablegen. Unfortunately I do...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote:
> On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote:
>> You need to specify sub-register == super-register, idx relationship.
>> See X86RegisterInfo.td:
>>
>> def x86_subreg_8bit : PatLeaf<(i32 1)>;
>> def x86_subreg_16bit : PatLeaf<(i32 2)>;
>> def x86_subreg_32bit : PatLeaf<(i32
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote:
> You need to specify sub-register == super-register, idx relationship.
> See X86RegisterInfo.td:
>
> def x86_subreg_8bit : PatLeaf<(i32 1)>;
> def x86_subreg_16bit : PatLeaf<(i32 2)>;
> def x86_subreg_32bit : PatLeaf<(i32 3)>;
>
> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
>