search for: superinstruction

Displaying 17 results from an estimated 17 matches for "superinstruction".

2011 Sep 20
0
[LLVMdev] VLIW Ports
...achineInstrBundle, which is essnetially a VLIW-style machine instruction which can store any MI on each "slot". After the scheduling phase has grouped MIs in bundles, it has to call MIB->pack() method, which takes operands from the MIs in the "slots" and transfers them to the superinstruction. From this point on the bundle is a normal machineinstruction which can be processed by other LLVM passes (such as register allocation). The idea was to make a framework on top of which VLIW/ILP scheduling could be studies using LLVM. It is not completely finished, but it is more or less usable an...
2011 Sep 19
4
[LLVMdev] VLIW Ports
Has anyone attempted the port of LLVM to a VLIW architecture? Is there any publication about it? TIA -- Evandro Menezes Austin, TX emenezes at codeaurora.org Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
2011 Oct 06
3
[LLVMdev] VLIW Ports
...hich is essnetially a VLIW-style machine > instruction which can store any MI on each "slot". After the scheduling > phase has grouped MIs in bundles, it has to call MIB->pack() method, > which takes operands from the MIs in the "slots" and transfers them to > the superinstruction. From this point on the bundle is a normal > machineinstruction which can be processed by other LLVM passes (such as > register allocation). > > The idea was to make a framework on top of which VLIW/ILP scheduling > could be studies using LLVM. It is not completely finished, but it...
2011 Oct 21
0
[LLVMdev] VLIW Ports
...is essnetially a VLIW-style machine > instruction which can store any MI on each "slot". After the > scheduling phase has grouped MIs in bundles, it has to call > MIB->pack() method, which takes operands from the MIs in the "slots" > and transfers them to the superinstruction. From this point on the > bundle is a normal machineinstruction which can be processed by other > LLVM passes (such as register allocation). > > The idea was to make a framework on top of which VLIW/ILP scheduling > could be studies using LLVM. It is not completely finished, but...
2011 Oct 22
3
[LLVMdev] VLIW Ports
...a VLIW-style machine >> instruction which can store any MI on each "slot". After the >> scheduling phase has grouped MIs in bundles, it has to call >> MIB->pack() method, which takes operands from the MIs in the "slots" >> and transfers them to the superinstruction. From this point on the >> bundle is a normal machineinstruction which can be processed by other >> LLVM passes (such as register allocation). >> >> The idea was to make a framework on top of which VLIW/ILP scheduling >> could be studies using LLVM. It is not compl...
2011 Oct 24
3
[LLVMdev] VLIW Ports
...a VLIW-style machine >> instruction which can store any MI on each "slot". After the >> scheduling phase has grouped MIs in bundles, it has to call >> MIB->pack() method, which takes operands from the MIs in the "slots" >> and transfers them to the superinstruction. From this point on the >> bundle is a normal machineinstruction which can be processed by other >> LLVM passes (such as register allocation). >> >> The idea was to make a framework on top of which VLIW/ILP scheduling >> could be studies using LLVM. It is not compl...
2011 Oct 24
0
[LLVMdev] VLIW Ports
...hine >>> instruction which can store any MI on each "slot". After the >>> scheduling phase has grouped MIs in bundles, it has to call >>> MIB->pack() method, which takes operands from the MIs in the "slots" >>> and transfers them to the superinstruction. From this point on the >>> bundle is a normal machineinstruction which can be processed by other >>> LLVM passes (such as register allocation). >>> >>> The idea was to make a framework on top of which VLIW/ILP scheduling >>> could be studies using L...
2011 Oct 24
2
[LLVMdev] VLIW Ports
...hine >>> instruction which can store any MI on each "slot". After the >>> scheduling phase has grouped MIs in bundles, it has to call >>> MIB->pack() method, which takes operands from the MIs in the "slots" >>> and transfers them to the superinstruction. From this point on the >>> bundle is a normal machineinstruction which can be processed by other >>> LLVM passes (such as register allocation). >>> >>> The idea was to make a framework on top of which VLIW/ILP scheduling >>> could be studies using L...
2011 Oct 24
3
[LLVMdev] VLIW Ports
...t;> instruction which can store any MI on each "slot". After the >>>> scheduling phase has grouped MIs in bundles, it has to call >>>> MIB->pack() method, which takes operands from the MIs in the "slots" >>>> and transfers them to the superinstruction. From this point on the >>>> bundle is a normal machineinstruction which can be processed by other >>>> LLVM passes (such as register allocation). >>>> >>>> The idea was to make a framework on top of which VLIW/ILP scheduling >>>> coul...
2011 Oct 25
0
[LLVMdev] VLIW Ports
...gt; instruction which can store any MI on each "slot". After the > >>> scheduling phase has grouped MIs in bundles, it has to call > >>> MIB->pack() method, which takes operands from the MIs in the "slots" > >>> and transfers them to the superinstruction. From this point on the > >>> bundle is a normal machineinstruction which can be processed by other > >>> LLVM passes (such as register allocation). > >>> > >>> The idea was to make a framework on top of which VLIW/ILP scheduling > >>>...
2011 Oct 22
0
[LLVMdev] VLIW Ports
...machine >>> instruction which can store any MI on each "slot". After the >>> scheduling phase has grouped MIs in bundles, it has to call >>> MIB->pack() method, which takes operands from the MIs in the "slots" >>> and transfers them to the superinstruction. From this point on the >>> bundle is a normal machineinstruction which can be processed by other >>> LLVM passes (such as register allocation). >>> >>> The idea was to make a framework on top of which VLIW/ILP scheduling >>> could be studies using LLVM....
2011 Oct 25
2
[LLVMdev] VLIW Ports
...gt; instruction which can store any MI on each "slot". After the > >>> scheduling phase has grouped MIs in bundles, it has to call > >>> MIB->pack() method, which takes operands from the MIs in the "slots" > >>> and transfers them to the superinstruction. From this point on the > >>> bundle is a normal machineinstruction which can be processed by other > >>> LLVM passes (such as register allocation). > >>> > >>> The idea was to make a framework on top of which VLIW/ILP scheduling > >>>...
2011 Oct 25
0
[LLVMdev] VLIW Ports
...gt;> instruction which can store any MI on each "slot". After the >>>> scheduling phase has grouped MIs in bundles, it has to call >>>> MIB->pack() method, which takes operands from the MIs in the "slots" >>>> and transfers them to the superinstruction. From this point on the >>>> bundle is a normal machineinstruction which can be processed by >>>> other LLVM passes (such as register allocation). >>>> >>>> The idea was to make a framework on top of which VLIW/ILP >>>> scheduling coul...
2011 Oct 25
0
[LLVMdev] VLIW Ports
...struction which can store any MI on each "slot". After the >>>>> scheduling phase has grouped MIs in bundles, it has to call >>>>> MIB->pack() method, which takes operands from the MIs in the "slots" >>>>> and transfers them to the superinstruction. From this point on the >>>>> bundle is a normal machineinstruction which can be processed by other >>>>> LLVM passes (such as register allocation). >>>>> >>>>> The idea was to make a framework on top of which VLIW/ILP scheduling >>&...
2011 Oct 26
2
[LLVMdev] VLIW Ports
...ruction which can store any MI on each "slot". After the >>>>> scheduling phase has grouped MIs in bundles, it has to call >>>>> MIB->pack() method, which takes operands from the MIs in the "slots" >>>>> and transfers them to the superinstruction. From this point on the >>>>> bundle is a normal machineinstruction which can be processed by >>>>> other LLVM passes (such as register allocation). >>>>> >>>>> The idea was to make a framework on top of which VLIW/ILP >>>>...
2011 Oct 26
0
[LLVMdev] VLIW Ports
...ruction which can store any MI on each "slot". After the >>>>> scheduling phase has grouped MIs in bundles, it has to call >>>>> MIB->pack() method, which takes operands from the MIs in the "slots" >>>>> and transfers them to the superinstruction. From this point on the >>>>> bundle is a normal machineinstruction which can be processed by >>>>> other LLVM passes (such as register allocation). >>>>> >>>>> The idea was to make a framework on top of which VLIW/ILP >>>>...
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
...hich is essnetially a VLIW-style machine > instruction which can store any MI on each "slot". After the scheduling > phase has grouped MIs in bundles, it has to call MIB->pack() method, > which takes operands from the MIs in the "slots" and transfers them to > the superinstruction. From this point on the bundle is a normal > machineinstruction which can be processed by other LLVM passes (such as > register allocation). > > The idea was to make a framework on top of which VLIW/ILP scheduling > could be studies using LLVM. It is not completely finished, but it i...