search for: sunkaddr262

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2016 Oct 10
2
[arm, aarch64] Alignment checking in interleaved access pass
...to have Halide generate this instead: %114 = shufflevector <16 x i32> %112, <16 x i32> %113, <16 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27> store <16 x i32> %114, <16 x i32>* %sunkaddr262 %115 = shufflevector <16 x i32> %112, <16 x i32> %113, <16 x i32> <i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> store <16 x i32> %115, <16 x i32>* %scevgep241 With the changes from th...
2016 Oct 10
2
[arm, aarch64] Alignment checking in interleaved access pass
Hi Renato, Thank you for the answers! First, let me clarify a couple of things and give some context. The patch it looking at VSTn, rather than VLDn (stores seem to be somewhat harder to get the "right" patterns, the pass is doing a good job for loads already) The examples you gave come mostly from loop vectorization, which, as I understand it, was the reason for adding the