search for: subwords

...to implement them in LLVM. I asked similar question before: http://lists.cs.uiuc.edu/pipermail/llvmdev/2005- May/004001.html Because I still don't have a satisfying solution now, I try to elaborate it again. Pardon. All registers are 128-bit. Each register can be divided into four 32-bit subwords. Each subword can be independently read and written. A symbolic name is given to each subword: x, y, z, w. MUL r0.xyz, r1.xyz, r2.xxx SUB r0.w, r3,y, r4.z ADD r5.xyzw, r0.xyzw, r2.xyzw MUL defines the three subwords of r0, and SUB defines the rest one. Note that ADD uses the four su...

Hi All, Some targets don't provide subword (e.g., i8 and i16 for a 32-bit machine) load and store instructions, so currently we have to custom-lower Load- and StoreSDNodes in our backends. For examples, see LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I believe it's possible to support this lowering in a target-agnostic fashion in LegalizeDAG.cpp, similar to

On 16 Jul 2011, at 03:34, Matt Johnson wrote: > Hi All, > Some targets don't provide subword (e.g., i8 and i16 for a 32-bit > machine) load and store instructions, so currently we have to > custom-lower Load- and StoreSDNodes in our backends. For examples, see > LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I > believe it's possible to

I'm targeting a machine that can only load and store aligned 64-bit words, but I'd like to be able to pack 8-, 16-, and 32-bit values into these words. Loads will require various shifts and masks; stores are more complicated. Does LLVM provide any support for such things? Is there an example target I can look at for ideas? Thanks, Preston -------------- next part -------------- An HTML

In downloads.html, link to downloads.xiph.org instead of SourceForge for source tarballs. Also includes a minor language fix in developers.html. --- developers.html | 2 +- download.html | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/developers.html b/developers.html index 149b6b5..87f0a9a 100644 --- a/developers.html +++ b/developers.html @@ -47,7 +47,7 @@

Chris Lattner wrote: > None, that documentation is out of date and doesn't make a ton of sense > for your application. I would suggest that you implement it in the > context of the SelectionDAG framework that all of the code generators > either currently use or are moving to. I updated the documentation > here:

Actually the problems that Tzu-Chien Chiu are encountering are similar to what should be done for generating SSE code in the X86 backend and also other SIMD instruction sets. I think LLVM neeeds to add instructions for permuting components, extracting and injecting elements in packed types. If the architecture has instructions which can do permutations for each instruction (for example

Each register is a 4-component (namely, r, g, b, a) vector register. They are actually defined as llvm packed [4xfloat]. The instruction: add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz Explaination: '.a' is a writemask. only the specified component will be update '.xxyy' and '.zzzz' are swizzle masks, specify the component permutation, simliar to the Intel SSE permutation

I scanned the website with linkchecker and found quite a lot of dead links. This commit fixes or removes them. --- developers.html | 2 +- documentation_tasks.html | 2 +- download.html | 12 ++++++------ faq.html | 2 +- features.html | 2 +- feeds/feed.xml | 8 ++++++++ format.html | 8 ++++----

I scanned the website with linkchecker and found quite a lot of dead links. This commit fixes or removes them. --- developers.html | 2 +- documentation_tasks.html | 2 +- download.html | 14 +++++++------- faq.html | 2 +- features.html | 2 +- feeds/feed.xml | 8 ++++++++ format.html | 8 ++++----