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subv
2009 Feb 11
1
[LLVMdev] Prevent node from being combined
...I need the shuffle mask in the machine instruction but sometimes if a
vector_shuffle can only return LHS or RHS, it's removed/combined so that I
cannot match vector_shuffle in the instruction selector.
If the vector_shuffle is combined, I have to write the instruction selector
like these:
def SUBvv: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1, imm:$mask1),
[sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0),
(vector_shuffle REG:$src1, REG:$src1, imm:$mask1)]
def SUBrv: MyInst<(ins REG:$src0, REG:$src1, imm:$mask1),
[sub REG:$src0,
(v...