search for: subtargetfeatures

...tudent/seerangv/DRAGONEGG_DIR/src/Backend.cpp:28:0: /gaia/class/student/seerangv/DRAGONEGG_DIR/src/Backend.cpp: In function ‘void CreateTargetMachine(const string&)’: /gaia/class/student/seerangv/DRAGONEGG_DIR/include/arm/dragonegg/Target.h:254:37: error: no matching function for call to ‘llvm::SubtargetFeatures::AddFeature(const char [5], bool)’ F.AddFeature("vfp3", TARGET_VFP3); \ ^ /gaia/class/student/seerangv/DRAGONEGG_DIR/src/Backend.cpp:464:3: note: in expansion of macro ‘LLVM_SET_SUBTARGET_FEATURES’ LLVM_SET_SUBTARGET_FEATURES(CPU, Features)...

I'm trying to enable/disable a target feature through clang. Here is how my target looks like // Esencia subtarget features //===----------------------------------------------------------------------===// def FeatureMul : SubtargetFeature<"mul", "HasMul", "true", "Enable hardware multiplier">; def FeatureDiv

I've been working on adding AVX to LLVM and have run across a number of questions. Here's the first one. In some ways AVX is "just another" SSE level. Having AVX implies you have SSE1-SSE4.2. However AVX is very different from SSE and there are a number of sub-features which may or may not be available on various implementations. So right now I've done this: def

On Apr 30, 2009, at 3:02 PM, David Greene wrote: > I've been working on adding AVX to LLVM and have run across a number > of > questions. Here's the first one. > > In some ways AVX is "just another" SSE level. Having AVX implies > you have > SSE1-SSE4.2. However AVX is very different from SSE and there are a > number > of sub-features which

Hi, I'd like to propose extending the supported syntax for AssemblerPredicates to allow sets of SubtargetFeatures to be listed, but where only one in the list has to be enabled for the predicate to be true. The condition string which forms a AssemblerPredicate already allows multiple features to be defined, separated by commas, and this means all of these features must be present. For example, "Feature1,...

ola, ive been looking at adding support for an -msave-args option for use on x86_64. the short explanation of it is that it makes x86_64 function prologues store their register arguments on the stack. the purpose of this is to make the arguments trivially accessible for things like stack traces with arguments. as per https://blogs.oracle.com/sherrym/entry/obtaining_function_arguments_on_amd64,

Hi, Justin PTX version in CUDA 4.0 has changed from 2.2 to 2.3. I add ptx23 subtarget and update a testcase. Is that O.K.? Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 -------------- next part -------------- Index: test/CodeGen/PTX/options.ll

Hi all, I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: name LDADDALX; class 872 microops 65535 I would have assumed that the microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong? Cheers, Tom #define GET_REGINFO_ENUM

...nd 1 of the Skylake Server microarchitecture are only 256-bits wide. 512-bit instructions using these ALUs must use both ports. See section 2.1 of Intel® 64 and IA-32 Architectures Optimization Reference Manual published October 2017. Implementation Plan: -Add prefer-avx256 and prefer-avx128 as SubtargetFeatures in X86.td not mapped to any CPU. -Add mprefer-avx256 and mprefer-avx128 and the corresponding -mno-prefer-avx128/256 options to clang's driver Options.td file. I believe this will allow clang to pass these straight through to the -target-feature attribute in IR. -Modify X86TTIImpl::getRegiste...

Hi, I think that def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", "HasVectorUAMem", "true", "Allow unaligned memory operands on vector/SIMD instructions">; should be switched-ON on AVX and AVX-512 instructions because: According to the AVX spec: "Most arithmetic and

...rectivePwr7, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>; During compilation the subtarget class (such as PPCSubtarget) is instantiated with the strings obtained from -mcpu and -mattr. ParseSubtargetFeatures then uses the -mcpu and -mattr values to determine which features to use for code generation. What seems problematic is that -mattr is the only way that the static features of the target processor can be overridden. It seems there must be a way for command-line parameters such as -fno-altivec to...

Hi, Justin Thansk, but I have a little concern though. I saw Chiou mentioned the compatibility issue of PTX on the mailing list. http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-March/038654.html In my PTX.td patch, def FeaturePTX23 : SubtargetFeature<"ptx23", "PTXVersion", PTX_VERSION_2_3", "Use PTX Language Version

...ptr(&g->triple_str), target_specific_cpu_args, target_specific_features, opt_level, reloc_mode, LLVMCodeModelDefault); char *ZigLLVMGetHostCPUName(void) { std::string str = sys::getHostCPUName(); return strdup(str.c_str()); } char *ZigLLVMGetNativeFeatures(void) { SubtargetFeatures features; StringMap<bool> host_features; if (sys::getHostCPUFeatures(host_features)) { for (auto &F : host_features) features.AddFeature(F.first(), F.second); } return strdup(features.getString().c_str()); } On this windows laptop that I am testing o...

Folks, I'm trying to compile the llvm-gcc-4.2-29 frontend at Ubunt 10.04 64bits following the steps described at README.LLVM conform the llvm/docs page. My commands: mkdir llvm-gcc-build cd llvm-gcc-build/ ../llvm-gcc-4.2-2.9.source/configure --disable-multilib --program-prefix=llvm- --enable-llvm=/home/bruno/projects/llvm/src/llvm-3.0.src/ --enable-languages=c,c++ make ENABLE_OPTIMIZED=1

On Tue, Apr 08, 2014 at 04:08:13PM +0400, Robert Khasanov wrote: > Hi Reid, > > Would you approve your patches r203146 and r202774 to be backported to > 3.4.1? They fix stability issues in x86 asm. > Hi Robert, I was able to merge r203146, but it used a c++11 feature: std::string::back() which I replaced with std::string::at(std::string::size() - 1). r202774 was not merged,

...SEL, Feature64Bit /*, Feature64BitRegs > > > > */]>; > > > > > > > > During compilation the subtarget class (such as PPCSubtarget) is > > > > instantiated with the strings obtained from -mcpu and -mattr. > > > > ParseSubtargetFeatures then uses the -mcpu and -mattr values to > > > > determine which features to use for code generation. > > > > > > > > What seems problematic is that -mattr is the only way that the static > > > > features of the target processor can be overridden. &g...

...atureSTFIWX, > > FeatureISEL, Feature64Bit /*, Feature64BitRegs > > */]>; > > > > During compilation the subtarget class (such as PPCSubtarget) is > > instantiated with the strings obtained from -mcpu and -mattr. > > ParseSubtargetFeatures then uses the -mcpu and -mattr values to > > determine which features to use for code generation. > > > > What seems problematic is that -mattr is the only way that the static > > features of the target processor can be overridden. > > > > It seems there must b...

AFAIK, there is no additional penalty for AMD processors. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chandler Carruth Sent: Monday, December 15, 2014 3:57 AM To: Demikhovsky, Elena Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets FWIW, this makes sense to me. I'd be interested to hear from

...ture64BitRegs > > > > > */]>; > > > > > > > > > > During compilation the subtarget class (such as PPCSubtarget) is > > > > > instantiated with the strings obtained from -mcpu and -mattr. > > > > > ParseSubtargetFeatures then uses the -mcpu and -mattr values to > > > > > determine which features to use for code generation. > > > > > > > > > > What seems problematic is that -mattr is the only way that the static > > > > > features of the target processor c...

...eatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, > FeatureISEL, Feature64Bit /*, Feature64BitRegs > */]>; > > During compilation the subtarget class (such as PPCSubtarget) is > instantiated with the strings obtained from -mcpu and -mattr. > ParseSubtargetFeatures then uses the -mcpu and -mattr values to > determine which features to use for code generation. > > What seems problematic is that -mattr is the only way that the static > features of the target processor can be overridden. > > It seems there must be a way for command-line param...