Displaying 20 results from an estimated 61 matches for "subtargetfeatur".
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subtargetfeature
2016 Oct 12
3
Dragon egg not recognizing Target ARM machine
...tudent/seerangv/DRAGONEGG_DIR/src/Backend.cpp:28:0:
/gaia/class/student/seerangv/DRAGONEGG_DIR/src/Backend.cpp: In function
‘void CreateTargetMachine(const string&)’:
/gaia/class/student/seerangv/DRAGONEGG_DIR/include/arm/dragonegg/Target.h:254:37:
error: no matching function for call to
‘llvm::SubtargetFeatures::AddFeature(const char [5], bool)’
F.AddFeature("vfp3", TARGET_VFP3);
\
^
/gaia/class/student/seerangv/DRAGONEGG_DIR/src/Backend.cpp:464:3: note: in
expansion of macro ‘LLVM_SET_SUBTARGET_FEATURES’
LLVM_SET_SUBTARGET_FEATURES(CPU, Feature...
2016 Mar 05
2
Enable / Disable a processor feature
I'm trying to enable/disable a target feature through clang.
Here is how my target looks like
// Esencia subtarget features
//===----------------------------------------------------------------------===//
def FeatureMul : SubtargetFeature<"mul", "HasMul", "true",
"Enable hardware multiplier">;
def FeatureDiv : SubtargetFeature<"div", "HasDiv", "true",
"Enable hardware divider&qu...
2009 Apr 30
2
[LLVMdev] RFC: AVX Feature Specification
...e.
In some ways AVX is "just another" SSE level. Having AVX implies you have
SSE1-SSE4.2. However AVX is very different from SSE and there are a number
of sub-features which may or may not be available on various implementations.
So right now I've done this:
def FeatureYMM : SubtargetFeature<"ymm", "X86YMM", "true", // Cray
"Enable YMM state">;
def FeatureVEX : SubtargetFeature<"vex", "X86VEX", "true", // Cray
"Enable VEX p...
2009 Apr 30
0
[LLVMdev] RFC: AVX Feature Specification
...SSE level. Having AVX implies
> you have
> SSE1-SSE4.2. However AVX is very different from SSE and there are a
> number
> of sub-features which may or may not be available on various
> implementations.
>
> So right now I've done this:
>
> def FeatureYMM : SubtargetFeature<"ymm", "X86YMM", "true", // Cray
> "Enable YMM state">;
> def FeatureVEX : SubtargetFeature<"vex", "X86VEX", "true", // Cray
> "...
2020 Feb 13
2
[RFC] Extension to TableGen's AssemblerPredicates to support combining features with ORs
Hi,
I'd like to propose extending the supported syntax for
AssemblerPredicates to allow sets of SubtargetFeatures to be listed, but
where only one in the list has to be enabled for the predicate to be true.
The condition string which forms a AssemblerPredicate already allows
multiple features to be defined, separated by commas, and this means all
of these features must be present. For example, "Feature...
2017 Apr 27
4
-msave-args backend support for x86_64
...d
===================================================================
--- lib/Target/X86/X86.td (revision 301500)
+++ lib/Target/X86/X86.td (working copy)
@@ -235,6 +235,9 @@
"LEA instruction with certain arguments is slow">;
def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
"INC and DEC instructions are slower than ADD and SUB">;
+def FeatureSaveArgs
+ : SubtargetFeature<"save-args", "SaveArgs", "true",
+...
2011 May 06
2
[LLVMdev] [PATCH ]Add Subtarget ptx23
...=====================================
--- lib/Target/PTX/PTX.td (revision 130978)
+++ lib/Target/PTX/PTX.td (working copy)
@@ -38,6 +38,10 @@
"Use PTX Language Version 2.2",
[FeaturePTX21]>;
+def FeaturePTX23 : SubtargetFeature<"ptx23", "PTXVersion", "PTX_VERSION_2_3",
+ "Use PTX Language Version 2.3",
+ [FeaturePTX22]>;
+
//===- PTX Shader Model ---------------------------------------------------===//...
2017 Sep 22
2
SchedClasses
...nInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "AArch64GenSubtargetInfo.inc"
#include "llvm/MC/MCSchedule.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/MC/MCSubtargetInfo.h"
#define GET_INSTRINFO_MC_DESC
#include "AArch64GenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "AArch64GenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "AArch64GenRegisterInfo.inc"
int m...
2017 Nov 01
5
RFC: [X86] Introducing command line options to prefer narrower vector instructions even when wider instructions are available
...nd 1 of the Skylake Server microarchitecture
are only 256-bits wide. 512-bit instructions using these ALUs must use both
ports. See section 2.1 of Intel® 64 and IA-32 Architectures Optimization
Reference Manual published October 2017.
Implementation Plan:
-Add prefer-avx256 and prefer-avx128 as SubtargetFeatures in X86.td not
mapped to any CPU.
-Add mprefer-avx256 and mprefer-avx128 and the corresponding
-mno-prefer-avx128/256 options to clang's driver Options.td file. I believe
this will allow clang to pass these straight through to the -target-feature
attribute in IR.
-Modify X86TTIImpl::getRegis...
2014 Dec 14
2
[LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets
Hi,
I think that
def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
"HasVectorUAMem", "true",
"Allow unaligned memory operands on vector/SIMD instructions">;
should be switched-ON on AVX and AVX-512 instructions because:
According to t...
2013 Jan 31
2
[LLVMdev] Getting command line options to affect subtarget features
The problem I'm trying to solve: Invoking clang on PowerPC with
-fno-altivec has no effect.
>From what I've been able to piece together, PPC.td specifies various
CPUs and the processor features available on each. So for example we
have:
def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
"Enable Altivec instructions">;
def : Processor<"pwr7", G5Itineraries,
[DirectivePwr7, FeatureAltivec,
FeatureMFOCRF, FeatureFSqr...
2011 May 07
2
[LLVMdev] [PATCH ]Add Subtarget ptx23
Hi, Justin
Thansk, but I have a little concern though. I saw Chiou mentioned the
compatibility issue of PTX on the mailing list.
http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-March/038654.html
In my PTX.td patch,
def FeaturePTX23 : SubtargetFeature<"ptx23", "PTXVersion", PTX_VERSION_2_3",
"Use PTX Language Version 2.3",
[FeaturePTX22]>;
I can only guess above statement means PTX23 is fully compatible with
PTX22. Is my guess ri...
2017 Sep 30
2
invalid code generated on Windows x86_64 using skylake-specific features
...ptr(&g->triple_str),
target_specific_cpu_args, target_specific_features, opt_level,
reloc_mode, LLVMCodeModelDefault);
char *ZigLLVMGetHostCPUName(void) {
std::string str = sys::getHostCPUName();
return strdup(str.c_str());
}
char *ZigLLVMGetNativeFeatures(void) {
SubtargetFeatures features;
StringMap<bool> host_features;
if (sys::getHostCPUFeatures(host_features)) {
for (auto &F : host_features)
features.AddFeature(F.first(), F.second);
}
return strdup(features.getString().c_str());
}
On this windows laptop that I am testing...
2012 Jan 27
2
[LLVMdev] llvm-gcc-4.2-2.9 compilation problems
...vm-gcc-4.2-2.9.source/configure --disable-multilib
--program-prefix=llvm-
--enable-llvm=/home/bruno/projects/llvm/src/llvm-3.0.src/
--enable-languages=c,c++
make ENABLE_OPTIMIZED=1
and i'm having the following errors:
../../llvm-gcc-4.2-2.9.source/gcc/llvm-backend.cpp:38:42: error:
llvm/Target/SubtargetFeature.h: No such file or directory
../../llvm-gcc-4.2-2.9.source/gcc/llvm-backend.cpp:42:40: error:
llvm/Target/TargetRegistry.h: No such file or directory
../../llvm-gcc-4.2-2.9.source/gcc/llvm-backend.cpp:50:41: error:
llvm/Support/StandardPasses.h: No such file or directory
These headers really aren...
2014 Apr 08
2
[LLVMdev] 3.4.1 Release Plans
...std::string::back() which I replaced with
std::string::at(std::string::size() - 1).
r202774 was not merged, because it is dependent on r198584 which adds the
X86AsmParser::is32BitMode() function. I don't think we would need to
backport all of r198584, maybe just the function and the Mode32Bit
SubtargetFeature. Could you take a look and let me know what you want
to do?
Thanks,
Tom
> Thanks,
> Robert
>
> понедельник, 7 апреля 2014 г. пользователь Tom Stellard написал:
>
> > Hi Robert,
> >
> > Can you ping the code owners about these patches. It might be good
> &g...
2013 Jan 31
2
[LLVMdev] Getting command line options to affect subtarget features
...fect.
> > > >
> > > > From what I've been able to piece together, PPC.td specifies various
> > > > CPUs and the processor features available on each. So for example we
> > > > have:
> > > >
> > > > def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec",
> > > > "true",
> > > > "Enable Altivec
> > > > instructions">;
> > > >
> > > > def : P...
2013 Jan 31
2
[LLVMdev] Getting command line options to affect subtarget features
...oking clang on PowerPC with
> > -fno-altivec has no effect.
> >
> > From what I've been able to piece together, PPC.td specifies various
> > CPUs and the processor features available on each. So for example we
> > have:
> >
> > def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec",
> > "true",
> > "Enable Altivec
> > instructions">;
> >
> > def : Processor<"pwr7", G5Itineraries,
>...
2014 Dec 15
2
[LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets
...upporting AMD processors which do support AVX to ensure that there isn't an undue runtime penalty for these.
On Sun, Dec 14, 2014 at 7:08 AM, Demikhovsky, Elena <elena.demikhovsky at intel.com<mailto:elena.demikhovsky at intel.com>> wrote:
Hi,
I think that
def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
"HasVectorUAMem", "true",
"Allow unaligned memory operands on vector/SIMD instructions">;
should be switched-ON on AVX and AVX-512 instructions because:
According to t...
2013 Jan 31
0
[LLVMdev] Getting command line options to affect subtarget features
...> > > > > From what I've been able to piece together, PPC.td specifies various
> > > > > CPUs and the processor features available on each. So for example we
> > > > > have:
> > > > >
> > > > > def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec",
> > > > > "true",
> > > > > "Enable Altivec
> > > > > instructions">;
> > > > >
> &g...
2013 Jan 31
0
[LLVMdev] Getting command line options to affect subtarget features
...oblem I'm trying to solve: Invoking clang on PowerPC with
> -fno-altivec has no effect.
>
> From what I've been able to piece together, PPC.td specifies various
> CPUs and the processor features available on each. So for example we
> have:
>
> def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec",
> "true",
> "Enable Altivec
> instructions">;
>
> def : Processor<"pwr7", G5Itineraries,
> [Direct...