Displaying 1 result from an estimated 1 matches for "subrv".
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subri
2009 Feb 11
1
[LLVMdev] Prevent node from being combined
...r.
If the vector_shuffle is combined, I have to write the instruction selector
like these:
def SUBvv: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1, imm:$mask1),
[sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0),
(vector_shuffle REG:$src1, REG:$src1, imm:$mask1)]
def SUBrv: MyInst<(ins REG:$src0, REG:$src1, imm:$mask1),
[sub REG:$src0,
(vector_shuffle REG:$src1, REG:$src1, imm:$mask1)]
def SUBvr: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1),
[sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0),
REG:$src1...