search for: subregisters

Hi all I have a hopefully not too stupid question about multi-level / mixed-effects modeling. I was trying to test a strategy from Crawley's 2013 R Book on a data set with the following structure: - dependent variable: CONSTRUCTION (a factor with 2 levels) - independent fixed effect: LENGTH (an integer in the interval [1, 61]) - random effects with the following hierarchical structure: MODE

Woud it be reasonable to assert that TargetRegisterInfo::isSubRegister() is a transitive relation? In other words, if A is a subregister of B and B is a subregister of C then A is a subregister of C. With this assumption, we could teach TableGen to sort registers topologically such that all the subregisters of R are numbered R+1, R+2, ... This produces better locality of reference and allows other optimizations in the backend code that deals in subregisters a lot. /jakob

Hello. In my TableGen back end description I need to use more than 32 (e.g., 128, 1024, etc) subregisters per register for my research SIMD processor. I have used so far with success 32 subregisters. However, when using 128 subregisters when I now give the command: llvm-tblgen -gen-register-info Connex.td I get an error message "error:Ran out of lanemask bits to represent subre...

On Feb 20, 2008, at 12:25 PM, David Greene wrote: > On Wednesday 20 February 2008 14:14, David Greene wrote: > >> I discovered this through an assert I put into some of my own >> code. I want >> to know if that assert is bogus or if there's a bug here. > > A little more information: the assert checks that after coalescing > two nodes, > all subregister

...reload per > basic block and retarget all the uses to use the result of the single > reload. It does not (yet) split intra-bb intervals. Ah, got it. Thanks. > > Also, in the ancient subregister coalescing code, there used to be > > an update > > of the SSARegMap to point subregisters to the superregister they were > > coalesced to (IIRC). That has since gone away. I used to use that > > in my > > code to return the correct live interval for a virtual register in > > the case > > where a subregister extract was coalesced. > > Right. That has...

I've been working on patches to improve subregister liveness tracking on llvm and I wanted to inform the llvm community about the overal design/motivation for them. I will send the patches to llvm-commits later today. Greetings Matthias Braun Subregisters in llvm ==================== Some targets can access registers in different ways resulting in wider or narrower accesses. For example on ARM NEON one of the single precision floating point registers is called 'S0'. You may also access 'D0' on arm which is the combination of 'S...

Evan, Can you explain the basic mechanics of the live interval splitting code? Is it all in LiveIntervalAnalysis.cpp under addIntervalsForSpills and child routines? What is it trying to do? Also, in the ancient subregister coalescing code, there used to be an update of the SSARegMap to point subregisters to the superregister they were coalesced to (IIRC). That has since gone away. I used to use that in my code to return the correct live interval for a virtual register in the case where a subregister extract was coalesced. That information appears to now be in RegSubIdxMap, which is local to run...

There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that appears to get tripped on targets that don't have subregisters defined: bool SubUsed = false; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) if (isUsed(SubReg)) { SubUsed = true; break; } assert(SubUsed && "Using a...

...al is spilled, it introduce a single reload per basic block and retarget all the uses to use the result of the single reload. It does not (yet) split intra-bb intervals. > > Also, in the ancient subregister coalescing code, there used to be > an update > of the SSARegMap to point subregisters to the superregister they were > coalesced to (IIRC). That has since gone away. I used to use that > in my > code to return the correct live interval for a virtual register in > the case > where a subregister extract was coalesced. Right. That has been removed because it's...

...M, Matthias Braun <mbraun at apple.com> wrote: > > > On Sep 8, 2016, at 6:37 AM, Alex Susu via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hello. > > In my TableGen back end description I need to use more than 32 (e.g., > 128, 1024, etc) subregisters per register for my research SIMD processor. I > have used so far with success 32 subregisters. > > > > However, when using 128 subregisters when I now give the command: > > llvm-tblgen -gen-register-info Connex.td > > I get an error message "error:Ran ou...

On Wednesday 20 February 2008 07:00:28 pm Evan Cheng wrote: > > In other words, after coalescing, should it be the case that > > subregister > > intervals contain at least all of the range information that was > > contained > > in any eliminated intervals when those eliminated intervals were > > coalesced > > to the subregister's superregister? >

...been working on patches to improve subregister liveness tracking on llvm and I wanted to inform the llvm community about the overal design/motivation for them. I will send the patches to llvm-commits later today. >> >> Greetings >> Matthias Braun >> >> >> Subregisters in llvm >> ==================== >> >> Some targets can access registers in different ways resulting in wider or >> narrower accesses. For example on ARM NEON one of the single precision >> floating point registers is called 'S0'. You may also access 'D0...

...g on patches to improve subregister liveness > tracking on llvm and I wanted to inform the llvm community about > the overal design/motivation for them. I will send the patches to > llvm-commits later today. > > Greetings > Matthias Braun > > > Subregisters in llvm > ==================== > > Some targets can access registers in different ways resulting in > wider or > narrower accesses. For example on ARM NEON one of the single precision > floating point registers is called 'S0'. You may also access 'D...

Hi, I am trying to take 16 bit memory reads and combine them to a single 32 bit read. I am having trouble to make the code simply read 32 bytes and the use the subregisters accordingly, without unnecessary copying. I have tried two techniques, in the MachineFunction: 1. replace the MachineOperands in the users of the data with the new register/subregister index. This yields an assert failure during VirtRegRewriter, in substPhysReg: "Invalid SubReg for physical...

Ugh. Management lobotomy kicked in. Need to RTFC better. On Thu, Feb 25, 2010 at 6:18 PM, Scott Michel <scooter.phd at gmail.com> wrote: > There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that > appears to get tripped on targets that don't have subregisters defined: > > bool SubUsed = false; > for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); > unsigned SubReg = *SubRegs; ++SubRegs) > if (isUsed(SubReg)) { > SubUsed = true; > break; > } >...

On Wednesday 20 February 2008 14:14, David Greene wrote: > I discovered this through an assert I put into some of my own code. I want > to know if that assert is bogus or if there's a bug here. A little more information: the assert checks that after coalescing two nodes, all subregister live intervals for the register coaelsced to now interfere with whatever the eliminated live

I am trying to locate a bug that affects my Blackfin backend. I am having some trouble understanding the semantics of def/kill flags on machine operands when using subregisters. I compile this function: define void @i56_ls(i56 %x) nounwind { store i56 %x, i56* @i56_s ret void } And get this initial machine code: Live Ins: %R0 %R1 %reg1025D<def> = MOVE %R1 %reg1024D<def> = MOVE %R0 %reg1026D<def> = MOVE %reg1025D %reg1027P<def> = LOAD32im...

...to improve subregister liveness tracking on >> llvm and I wanted to inform the llvm community about the overal >> design/motivation for them. I will send the patches to llvm-commits later >> today. >> >> Greetings >> Matthias Braun >> >> >> Subregisters in llvm >> ==================== >> >> Some targets can access registers in different ways resulting in wider or >> narrower accesses. For example on ARM NEON one of the single precision >> floating point registers is called 'S0'. You may also access 'D0'...

No, I wasn't having a management lobotomy moment. If the target's registers have no subregisters, SubUsed is false and the assert gets tripped. Ok, back to the original question: What was the original intent in this code (lines 186-193 in lib/CodeGen/RegisterScavenging.cpp)? -scooter On Thu, Feb 25, 2010 at 7:00 PM, Scott Michel <scooter.phd at gmail.com> wrote: > Ugh. Management...

Hi Tom, The output: Added VReg_64(explicit) Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64) is saying that VS_32 was added because VReg_64 was explicitly specified and that while inspecting VS_32, it noticed that every register in VS_32 was a subregister of a register from VReg_64 using a single common subregister index. I've added some more tracing to my local copy and