search for: subregindices

...>> Hello, >>>>> i am trying to construct a register of size 65536 bit by combining 2 >>>>> registers of 32768 bits. both the 32768 bit registers are different so i >>>>> have to use the following method >>>>> >>>>> let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs >>>>> = 1 in >>>>> >>>>> but i am getting following error.. >>>>> >>>>> error:Ran out of lanemask bits to represent subregister >>>>> sub_32768bit_hi_then_su...

I have made changes in 3 files: LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached here. Now i am getting following errors. which means registerinfo.inc file is not generated successfully. /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: no member named 'XMM8' in namespace 'llvm::X86' if ((RegNo >= X86::XMM8 && RegNo <=

Hello, i am trying to construct a register of size 65536 bit by combining 2 registers of 32768 bits. both the 32768 bit registers are different so i have to use the following method let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs = 1 in but i am getting following error.. error:Ran out of lanemask bits to represent subregister sub_32768bit_hi_then_sub_16384bit_hi_then_sub_32bit now how to increase lanemask bits? what changes are required in IntrinsicEmitter.cpp file?? P...

...Jul 14, 2017 at 8:33 PM, hameeza ahmed <hahmed2305 at gmail.com> wrote: > > Hello, > i am trying to construct a register of size 65536 bit by combining 2 > registers of 32768 bits. both the 32768 bit registers are different so i > have to use the following method > > let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs = 1 > in > > but i am getting following error.. > > error:Ran out of lanemask bits to represent subregister > sub_32768bit_hi_then_sub_16384bit_hi_then_sub_32bit > > now how to increase lanemask bits? what changes are requi...

...rzysztof I have seen similar question asked by you on llvm group. Could you please help me here to address this issue. i am trying to construct a register of size 65536 bit by combining 2 registers of 32768 bits. both the 32768 bit registers are different so i have to use the following method let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs = 1 in but i am getting following error.. error:Ran out of lanemask bits to represent subregister sub_32768bit_hi_then_sub_16384bit_hi_then_sub_8192bit_hi_then _sub_4096bit_hi_then_sub_2048bit_hi_then_sub_32bit_hi_then now how to increase lanem...

...oup. >> Could you please help me here to address this issue. >> >> i am trying to construct a register of size 65536 bit by combining 2 >> registers of 32768 bits. both the 32768 bit registers are different so i >> have to use the following method >> >> let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs = 1 >> in >> >> but i am getting following error.. >> >> error:Ran out of lanemask bits to represent subregister >> sub_32768bit_hi_then_sub_16384bit_hi_then_sub_8192bit_hi_ >> then_sub_4096bit_hi_then_sub...

...t;> wrote: >> >>> >>> Hello, >>> i am trying to construct a register of size 65536 bit by combining 2 >>> registers of 32768 bits. both the 32768 bit registers are different so i >>> have to use the following method >>> >>> let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs = >>> 1 in >>> >>> but i am getting following error.. >>> >>> error:Ran out of lanemask bits to represent subregister >>> sub_32768bit_hi_then_sub_16384bit_hi_then_sub_32bit >>> >&g...

i have loop index I. I want to increment it by 1. How to do this in registerinfo.td. I m trying following but getting error. let SubRegIndices = [sub_32bit, sub_32bit_hi], CoveredBySubRegs = 1 in { foreach I = 0-255 in { m=add(I,1); def R_#J#_REG64b_#I : R_P<"R_"#J#"_R64b_"#I, !shl(I,2), [!cast<R_P>("R_"#J#"_REG32b_"#I), !cast<R_PIM>("R_"#J#"_REG32b_"#m)]&gt...

...lectors. Thank you, -- Kenneth Waters P.S. If it helps, my register definitions look like, multiclass M68kDataReg<bits<3> num, string defn, string n> { def B : M68kReg<num, n>; def W : M68kRegWithSubregs<num, n, [!cast<Register>(defn # "B")]> { let SubRegIndices = [sub_byte]; } def L : M68kRegWithSubregs<num, n, [!cast<Register>(defn # "W")]> { let SubRegIndices = [sub_word]; } } defm D0 : M68kDataReg<0, "D0", "d0">; defm D1 : M68kDataReg<1, "D1", "d1">; -------------- next...

...Rf<bits<5> num, string n> : SparcReg<n> { let Num = num; } // Rd - Slots in the FP register file for 64-bit floating-point values. class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { let Num = num; let SubRegs = subregs; let SubRegIndices = [sub_even, sub_odd]; let CoveredBySubRegs = 1; } ...... // Mips CPU Registers class MipsGPRReg<bits<5> num, string n> : MipsReg<n> { let Num = num; }

...ddress this issue. >>>> >>>> i am trying to construct a register of size 65536 bit by combining 2 >>>> registers of 32768 bits. both the 32768 bit registers are different so i >>>> have to use the following method >>>> >>>> let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs = >>>> 1 in >>>> >>>> but i am getting following error.. >>>> >>>> error:Ran out of lanemask bits to represent subregister >>>> sub_32768bit_hi_then_sub_16384bit_hi_then_sub_8...

...rcReg<n> { > let Num = num; > } > // Rd - Slots in the FP register file for 64-bit floating-point values. > class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { > let Num = num; > let SubRegs = subregs; > let SubRegIndices = [sub_even, sub_odd]; > let CoveredBySubRegs = 1; > } > > ...... > // Mips CPU Registers > class MipsGPRReg<bits<5> num, string n> : MipsReg<n> { > let Num = num; > } > _______________________________________________ > LLVM Developers mail...

...i am trying to construct a register of size 65536 bit by >> combining 2 registers of 32768 bits. both the 32768 bit >> registers are different so i have to use the following >> method >> >> let SubRegIndices = [sub_32768bit, sub_32768bit_hi], >> CoveredBySubRegs = 1 in >> >> but i am getting following error.. >> >> error:Ran out of lanemask bits to represent subregister >> sub_32768bit_hi_then_sub_16384b...

On 9/28/2016 7:30 PM, Quentin Colombet wrote: > Out of curiosity, could describe why this is useful to have such precision in the liveness tracking? RDF is meant to allow optimizations across the whole function. As a result, registers may change between basic blocks, and there is code to recalculate it. Accuracy is required to avoid unnecessary block live-ins. For example, calculate live-ins

...t;8, "a">; def AB : MC6809Reg<9, "b">; def CC : MC6809Reg<10, "cc">; def DP : MC6809Reg<11, "dp">; def A0 : MC6809Reg<12, "0">; def AE : MC6809Reg<14, "e">; def AF : MC6809Reg<15, "f">; let SubRegIndices = [sub_hi_byte, sub_lo_byte], CoveredBySubRegs = 1 in { def AD : MC6809RegWithSubregs<0, "d", [AA,AB], ["a","b"]>; def AW : MC6809RegWithSubregs<6, "w", [AE,AF], ["e","f"]>; } let SubRegIndices = [sub_hi_word, sub_lo_word]...

Does anyone know exactly what ComposerIndices in Target.td is all about? I see just one place where it's used in X86 but it's not clear from the comments in Target.td and it's one usage, exactly what this feature is about. Tia. Reed

Hi All, If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si __attribute__ ((vector_size (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing

On Jan 9, 2012, at 10:00 AM, Jakob Stoklund Olesen wrote: > > On Jan 8, 2012, at 11:18 PM, Demikhovsky, Elena wrote: > >> I'll explain what we see in the code. >> 1. The caller saves XMM registers across the call if needed (according to DEFS definition). >> YMMs are not in the set, so caller does not take care. > > This is not how the register allocator

...> Enc, string n> : Register<n> { > - let Namespace = "BPF"; > +class Ri<bits<16> Enc, string n, list<Register> subregs> > + : RegisterWithSubRegs<n, subregs> { > let HWEncoding = Enc; > + let Namespace = "BPF"; > + let SubRegIndices = [sub_32]; > } > > -// Integer registers > -def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; > -def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; > -def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; > -def R3 : Ri< 3, "r3"&...

...;>, DwarfRegNum<[1]>; def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; ... ...which could be accessed as double regs in pairs: // Aliases of the R* registers used to hold 64-bit int values (doubles). let SubRegIndices = [subreg_loreg, subreg_hireg] in { def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; So R2:R3 are sub...