search for: subregindex

Hi all, I just committed r183020 and r183061, that add Size/Offset information to SubRegIndex. If you maintain an out-of-tree target, there are a few things to change: - the SubRegIndex class has a new mandatory argument, representing the Size (in bits) covered by the index. If it's not meaningful (ex: same index for different kinds of registers), set it to -1 (though I believe this i...

Do your 32768 registers also have sub registers? I can't tell you exactly what to change. I'm not familiar with the code. I would just be running grep or something. ~Craig On Fri, Jul 14, 2017 at 10:23 AM, hameeza ahmed <hahmed2305 at gmail.com> wrote: > Thank you so much. I think there is no issue with my definitions since i > have to use larger registers i.e 65536 bit

I have made changes in 3 files: LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached here. Now i am getting following errors. which means registerinfo.inc file is not generated successfully. /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: no member named 'XMM8' in namespace 'llvm::X86' if ((RegNo >= X86::XMM8 && RegNo <=

Does anyone know exactly what ComposerIndices in Target.td is all about? I see just one place where it's used in X86 but it's not clear from the comments in Target.td and it's one usage, exactly what this feature is about. Tia. Reed

Hi, I think I've found a bug in this method. I ran it on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. For the def-operand, with a subregindex, an implicit-use operand was added with this code: VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands()); MI.addOperand(MachineOperand::CreateReg(VirtReg, false, // isDef...

On Oct 7, 2011, at 8:14 AM, Jonas Paulsson wrote: > Hi, > > I think I've found a bug in this method. > > I ran it on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. > > For the def-operand, with a subregindex, an implicit-use operand was added with this code: > > VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands()); > MI.addOperand(MachineOperand::CreateReg(VirtReg, > false...

...escribe the detailed instruction encode format. It needs (regFile, regNum, subRegNum, width, type, addrMode, hStride, vStride) to describe a register. I have attached my first version RegisterInfo.td. And I also have a question about the attached RegisterInfo.td file. Do I have to define different SubRegIndex like below to make TableGen works correctly? foreach Index = 0-15 in { def subd#Index :SubRegIndex<32, !shl(Index, 5)>; //used as SubRegIndex when declaring gpr_d_simd8 def subw#Index: SubRegIndex<16, !shl(Index, 4)>; //used as SubRegIndex when declaring gpr_w_simd8 ... } If anythi...

...rTuple is kind of expressing register alias in RegisterInfo.td file. I am not sure whether I understand it correctly. My first trial was like below(to make things simple, I remove some WORD/QWORD register class): let Namespace = "IntelGPU" in { foreach Index = 0-15 in { def sub#Index : SubRegIndex<32, !shl(Index, 5)>; } } class IntelGPUReg<string n, bits<13> regIdx> : Register<n> { bits<2> HStride; bits<1> regFile; let Namespace = "IntelGPU"; let HWEncoding{12-0} = regIdx; let HWEncoding{15} = regFile; } // here I define the whole...

...class with these registers and > only using that register class as an operand in the instructions where it > is legal. > You then set as sub registers what you want to represent as the hi and lo > registers for those 64bit registers. > > So something like this: > def lo_comp : SubRegIndex; > def hi_comp : SubRegIndex; > def R1 : Register<1>; > def R2 : Register<2>; > def R3 : Register<1>; > def R4 : Register<2>; > def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; > > This says that D1 is a register with two component...

...an be done by declaring a register class with these registers and only using that register class as an operand in the instructions where it is legal. You then set as sub registers what you want to represent as the hi and lo registers for those 64bit registers. So something like this: def lo_comp : SubRegIndex; def hi_comp : SubRegIndex; def R1 : Register<1>; def R2 : Register<2>; def R3 : Register<1>; def R4 : Register<2>; def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; This says that D1 is a register with two components, lo and hi. When you allocate D1, you...

On Mips 32 there is traditionally a 64 bit HI/LO register for the result of multiplying two 64 bit numbers. There are corresponding instructions to load the LO and HI parts into individual 32 registers. On Mips with the DSP ASE (an application specific extension), there are actual 4 such pairs of registers. Is there a way to have special purpose 64 bit registers without actually having to

...registers and only using that register class as an operand in the > instructions where it is legal. > You then set as sub registers what you want to represent as the hi > and lo registers for those 64bit registers. > > So something like this: > def lo_comp : SubRegIndex; > def hi_comp : SubRegIndex; > def R1 : Register<1>; > def R2 : Register<2>; > def R3 : Register<1>; > def R4 : Register<2>; > def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; > > This says that D1 is a...

...an be done by declaring a register class with these registers and only using that register class as an operand in the instructions where it is legal. You then set as sub registers what you want to represent as the hi and lo registers for those 64bit registers. So something like this: def lo_comp : SubRegIndex; def hi_comp : SubRegIndex; def R1 : Register<1>; def R2 : Register<2>; def R3 : Register<1>; def R4 : Register<2>; def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; This says that D1 is a register with two components, lo and hi. When you allocate D1, you...

...and >> only using that register class as an operand in the instructions where it >> is legal. >> You then set as sub registers what you want to represent as the hi and lo >> registers for those 64bit registers. >> >> So something like this: >> def lo_comp : SubRegIndex; >> def hi_comp : SubRegIndex; >> def R1 : Register<1>; >> def R2 : Register<2>; >> def R3 : Register<1>; >> def R4 : Register<2>; >> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; >> >> This says that D1...

...6809RegWithSubregs<bits<4> num, string n, list<Register> subregs, list<string> alt = []> : RegisterWithSubRegs<n, subregs> { field bits<4> Num = num; let Namespace = "MC6809"; let HWEncoding{3-0} = num; let AltNames = alt; } def sub_lo_byte : SubRegIndex<8, 8>; def sub_hi_byte : SubRegIndex<8>; def sub_lo_word : SubRegIndex<16, 16>; def sub_hi_word : SubRegIndex<16>; //===----------------------------------------------------------------------===// // Registers //===----------------------------------------------------------...

...ing that register class as an operand in the >> instructions where it is legal. >> You then set as sub registers what you want to represent as the >> hi and lo registers for those 64bit registers. >> >> So something like this: >> def lo_comp : SubRegIndex; >> def hi_comp : SubRegIndex; >> def R1 : Register<1>; >> def R2 : Register<2>; >> def R3 : Register<1>; >> def R4 : Register<2>; >> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; >> &gt...

...Date: Wed, 12 Oct 2011 09:14:52 -0700 CC: llvmdev at cs.uiuc.edu To: jnspaulsson at hotmail.com On Oct 7, 2011, at 8:14 AM, Jonas Paulsson wrote:Hi, I think I've found a bug in this method. I ran it on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. For the def-operand, with a subregindex, an implicit-use operand was added with this code: VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands()); MI.addOperand(MachineOperand::CreateReg(VirtReg, false, // isDef...

...and >> only using that register class as an operand in the instructions where it is >> legal. >> You then set as sub registers what you want to represent as the hi and lo >> registers for those 64bit registers. >> >> So something like this: >> def lo_comp : SubRegIndex; >> def hi_comp : SubRegIndex; >> def R1 : Register<1>; >> def R2 : Register<2>; >> def R3 : Register<1>; >> def R4 : Register<2>; >> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; >> >> This says that D1...

...ass as an operand in the instructions where > it is > >> legal. > >> You then set as sub registers what you want to represent as the hi and > lo > >> registers for those 64bit registers. > >> > >> So something like this: > >> def lo_comp : SubRegIndex; > >> def hi_comp : SubRegIndex; > >> def R1 : Register<1>; > >> def R2 : Register<2>; > >> def R3 : Register<1>; > >> def R4 : Register<2>; > >> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; > &...

...egisterInfo.td > +++ b/lib/Target/BPF/BPFRegisterInfo.td > @@ -11,31 +11,63 @@ > // Declarations that describe the BPF register file > //===----------------------------------------------------------------------===// > > +let Namespace = "BPF" in { > + def sub_32 : SubRegIndex<32>; > +} > + > +class Wi<bits<16> Enc, string n> : Register<n> { > + let HWEncoding = Enc; > + let Namespace = "BPF"; > +} > + > // Registers are identified with 4-bit ID numbers. > // Ri - 64-bit integer registers > -class Ri<...