Displaying 16 results from an estimated 16 matches for "subregclasslist".
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...SI, DI,
> > R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> > [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> > R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
> >
> >
> > class GR16_ ..... {
> > let SubRegClassList = [GR8];
> > }
>
> Right. Subreg index starts from 1. This ought to be fixed but it's not
> (yet).
>
> >
> >
> > The getSubRegisterRegClass uses SubIdx - 1;
> >
> > so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because
> >...
2008 Oct 18
2
[LLVMdev] INSERT_SUBREG node.
...nd high
> > parts using INSERT_SUBREG.
> >
> > The workaround is to declare the same SubRegClass twice while
> > declaring
> > the SuperRegisterClass. i.e.
> >
> > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> > let SubRegClassList = [FSR8, FSR8]; // HERE.
> > }
>
> This is a bug, probably in tablegen. Unfortunately I don't have the
> time to fix it. But please file a bug about this. Hopefully someone
> will fix it soon.
>
> Thanks,
>
> Evan
>
PR2916 filed.
Though I did not quit...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
...parts using INSERT_SUBREG.
>>>
>>> The workaround is to declare the same SubRegClass twice while
>>> declaring
>>> the SuperRegisterClass. i.e.
>>>
>>> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
>>> let SubRegClassList = [FSR8, FSR8]; // HERE.
>>> }
>>
>> This is a bug, probably in tablegen. Unfortunately I don't have the
>> time to fix it. But please file a bug about this. Hopefully someone
>> will fix it soon.
>>
>> Thanks,
>>
>> Evan
>>
>...
2008 Oct 20
2
[LLVMdev] INSERT_SUBREG node.
...> > > The workaround is to declare the same SubRegClass twice while
> > > > declaring
> > > > the SuperRegisterClass. i.e.
> > > >
> > > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> > > > let SubRegClassList = [FSR8, FSR8]; // HERE.
> > > > }
> > >
> > > This is a bug, probably in tablegen. Unfortunately I don't have
> > > the
> > > time to fix it. But please file a bug about this. Hopefully
> > > someone
> > > will fix it soo...
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...;(i32 0)>;
def : SubRegSet<0, [AX, CX, DX, BX, SP, BP, SI, DI,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
[AL, CL, DL, BL, SPL, BPL, SIL, DIL,
R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
class GR16_ ..... {
let SubRegClassList = [GR8];
}
Refer to below functions in ScheduleDAGEmit.cpp:
-----------------------------------------------
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister
TargetRegisterInfo::regclass_i...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...Set<0, [AX, CX, DX, BX, SP, BP, SI, DI,
> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
>
>
> class GR16_ ..... {
> let SubRegClassList = [GR8];
> }
Right. Subreg index starts from 1. This ought to be fixed but it's not
(yet).
>
>
> The getSubRegisterRegClass uses SubIdx - 1;
>
> so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because
> getSubRegisterRegClass will fail.(GR16_ does not have a...
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...ters class and want to set both the lo and high
> parts using INSERT_SUBREG.
>
> The workaround is to declare the same SubRegClass twice while
> declaring
> the SuperRegisterClass. i.e.
>
> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> let SubRegClassList = [FSR8, FSR8]; // HERE.
> }
This is a bug, probably in tablegen. Unfortunately I don't have the
time to fix it. But please file a bug about this. Hopefully someone
will fix it soon.
Thanks,
Evan
>
>
> SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>;
> SubRegSet : &...
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
...;"FSR0", [FSR0H, FSR0L]>;
def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L,
FSR1H]>;
def FSR16RC : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]> {
let SubRegClassList = [FSR8RC];
}
in my case I want to insert two values, which are available in register
types of FSR8RC, into a register type of FSR16RC.
when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in
> v4= insert_subreg implicit_def, v1, 0
the following function returns an incorrect...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
...ased on your comments. :-) It should be possible to specify two FSR0
>> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
>> workaround you described:
>>
>>
>> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
>> let SubRegClassList = [FSR8, FSR8]; // HERE.
>> }
>>
> It is currently possible.
I am confused. Is what you described in PR2916 an issue or not?
Evan
>
>
> - Sanjiv
>
>>
>> Evan
>>
>>>
>>>
>>> - Sanjiv
>>>
>>>
>>> _...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
...R0L]>;
> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
>
> def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L,
> FSR1H]>;
>
> def FSR16RC : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]> {
> let SubRegClassList = [FSR8RC];
> }
>
> in my case I want to insert two values, which are available in
> register
> types of FSR8RC, into a register type of FSR16RC.
>
> when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in
>
>> v4= insert_subreg implicit_def, v1, 0
>...
2008 Oct 20
1
[LLVMdev] INSERT_SUBREG node.
...should be possible to specify two FSR0
> >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
> >> workaround you described:
> >>
> >>
> >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> >> let SubRegClassList = [FSR8, FSR8]; // HERE.
> >> }
> >>
> > It is currently possible.
>
> I am confused. Is what you described in PR2916 an issue or not?
>
is specifying the same subregclass two times okay? or do we need to
cleanup the implementation so that you specify a SubRegCl...
2010 Aug 29
2
[LLVMdev] Register design decision for backend
...lt;"r1">, DwarfRegNum<[1]>;
// reg pairs
def R1R0 : RegisterWithSubRegs<"r0", [R0, R1]>, DwarfRegNum<[0]>;
def GPR8 : RegisterClass<"TEST", [i8], 8, [R0, R1]>;
def WDREGS : RegisterClass<"TEST", [i16], 16, [R1R0]>
{
let SubRegClassList = [GPR8, GPR8];
}
This way i could work with register pairs easily, for example storing i16
data inside the WDREGS class or i32 inside 2 WDREGS registers, etc. I
thought everything was going fine until i tried to do a 16 bit addition. The
addition instruction only works with 8 bit regs (GPR8 class...
2010 Aug 31
0
[LLVMdev] Register design decision for backend
...[1]>;
>
> // reg pairs
> def R1R0 : RegisterWithSubRegs<"r0", [R0, R1]>, DwarfRegNum<[0]>;
>
> def GPR8 : RegisterClass<"TEST", [i8], 8, [R0, R1]>;
> def WDREGS : RegisterClass<"TEST", [i16], 16, [R1R0]>
> {
> let SubRegClassList = [GPR8, GPR8];
> }
>
> This way i could work with register pairs easily, for example storing i16
> data inside the WDREGS class or i32 inside 2 WDREGS registers, etc. I
> thought everything was going fine until i tried to do a 16 bit addition. The
> addition instruction only work...
2008 Oct 02
0
[LLVMdev] INSERT_SUBREG node.
On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
> What’s the value produced by an INSERT_SUBREG node? Is it a chain?
No, insert_subreg returns a value:
v1 = insert_subreg v2, v3, idx
v1 and v2 will have the same type, e.g. i16, and v3 must have a sub-
register type, e.g. i8.
> Can I use to set a superreg of i16 type with two i8 values, and use
> the supperreg as
2008 Oct 02
2
[LLVMdev] INSERT_SUBREG node.
What's the value produced by an INSERT_SUBREG node? Is it a chain?
Can I use to set a superreg of i16 type with two i8 values, and use the
supperreg as an operand somewhere else?
- Sanjiv
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2010 Aug 31
2
[LLVMdev] Register design decision for backend
...g pairs
>> def R1R0 : RegisterWithSubRegs<"r0", [R0, R1]>, DwarfRegNum<[0]>;
>>
>> def GPR8 : RegisterClass<"TEST", [i8], 8, [R0, R1]>;
>> def WDREGS : RegisterClass<"TEST", [i16], 16, [R1R0]>
>> {
>> let SubRegClassList = [GPR8, GPR8];
>> }
>>
>> This way i could work with register pairs easily, for example storing i16
>> data inside the WDREGS class or i32 inside 2 WDREGS registers, etc. I
>> thought everything was going fine until i tried to do a 16 bit addition. The
>> additi...