search for: subreg_to_reg

...ed physical register *** - function: autogen_SD24657 - basic block: BB 0x2662d60 (BB#0) - instruction: %XMM0<def> = MOV64toPQIrr %RAX<kill> - operand 1: %RAX<kill> LLVM ERROR: Found 1 machine code errors. This happens because, on entry to the pass, we have %RAX<def> = SUBREG_TO_REG 0, %R9D, 4 %XMM0<def> = MOV64toPQIrr %RAX<kill> The pass converts (around about line 132 in ExpandPostRAPseudos.cpp) the SUBREG_TO_REG pseudo op to %EAX<def> = MOV32rr %R9D Because of "-mcpu-atom", post RA scheduling is enabled, so is po...

...r for the address (which is zero-extended, effectively > ignoring the metadata bits). As a side note, GCC does emit the second > snippet as expected. > > > Looking at the TableGen files I found two problems: > > 1. The AND of the address with 0xffffffff is replaced with > SUBREG_TO_REG(MOV32rr (EXTRACT_SUBREG ...)) in > lib/Target/X86/X86InstrCompiler.td (line 1326). That MOV32rr emits an > explicit mov instruction later. I think I need to replace this with > (i32 (EXTRACT_SUBREG ...)) to get rid of the mov, but that produces a > 32-bit value, which leads me to th...

...arate mov, but by using a subregister for the address (which is zero-extended, effectively ignoring the metadata bits). As a side note, GCC does emit the second snippet as expected. Looking at the TableGen files I found two problems: 1. The AND of the address with 0xffffffff is replaced with SUBREG_TO_REG(MOV32rr (EXTRACT_SUBREG ...)) in lib/Target/X86/X86InstrCompiler.td (line 1326). That MOV32rr emits an explicit mov instruction later. I think I need to replace this with (i32 (EXTRACT_SUBREG ...)) to get rid of the mov, but that produces a 32-bit value, which leads me to the next, more general...

...there any easy way to do this? I understand that %0 comes from a live-in value which is defined from outside of the function. I could, at the ISelLowering stage when seeing an ADD, replace the “%0” with a i32 constant 0, but I don’t feel like this is the right approach. Should I try to look into SUBREG_TO_REG/INSERT_REG here? Or any other thoughts? Thanks, - Cheng-Chih

I'm trying to fix a bug in the PowerPC SPE backend that prevents a bunch of FreeBSD ports from building, including gtk20. The attached file, generated from the following C source, triggers the "Def == PreviousDef" assertion in isNopCopy(): typedef float a; typedef struct { a b, c; } complex; d(complex *e, complex *h) { double f = h->c, g = h->b; i(g); e->c = g *

...m when helping to land a scheduler .td file that my colleague had written. The problem that came up was that a multiply/add pair was not combined into an madd, but just for our CPU. Upon digging into it, the problem turned out to be that '(instregex "^SUB" ...' was matching "SUBREG_TO_REG" and incorrectly increasing the schedule length. I removed the overly aggressive match, but I noticed that there were lots of instructions that matched multiple regex patterns in InstegexOp::apply in utils/TableGen/CodeGenSchedule. I modified the apply method to output <idx, pat> pairs...

...in function with a printf and a return inside it): # Machine code for function main: SSA BB#0: derived from LLVM BB %entry ADJCALLSTACKDOWN64 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use> %vreg2<def> = MOV32ri64 <ga:@str>; GR32:%vreg2 %vreg3<def> = SUBREG_TO_REG 0, %vreg2<kill>, 4; GR64:%vreg3 GR32:%vreg2 %RDI<def> = COPY %vreg3; GR64:%vreg3 CALL64pcrel32 <ga:@puts>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSP<imp-def>, %EAX<imp-def> ADJCALLSTACKUP64 0, 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead&g...

...:getNodePriority() (in CodeGen/SelectionDAG/ScheduleDAGRRList.cpp) normally returns the SethiUllmanNumber for a node, but there's a few special cases. ISD::TokenFactor and ISD::CopyToReg return a 0, to push them closer to their uses, and similarly for TargetOpcode::EXTRACT_SUBREG, TargetOpcode::SUBREG_TO_REG, and TargetOpcode::INSERT_SUBREG. There is also a special case for instructions that are the end of a computational chain, or at the beginning, based on if the instruction has 0 predecessors or 0 successors. Our fence instruction has 2 (constant) predecessors and no successors. This causes getNode...

+Matthias > On Mar 2, 2018, at 6:42 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > >> Known limitations on X86 processors >> ----------------------------------- >> >> 1) Partial register updates versus full register updates. >> <snip> > > MachineOperand handles this. You just need to create the machine instrs. > >

...steps back to the first use of the constant. Here's a snippet of MIR output that illustrates the problem: %19:gr64 = ADD64ri8 %18, 8, implicit-def dead %eflags; GR64:%19,%18 dbg:destroy-after-foreach.swift:2:7 %20:gr32 = MOV32ri64 1; GR32:%20 dbg:destroy-after-foreach.swift:1:44 %21:gr64 = SUBREG_TO_REG 0, killed %20, sub_32bit; GR64:%21 GR32:%20 dbg:destroy-after-foreach.swift:1:44 %rdi = COPY %21; GR64:%21 dbg:destroy-after-foreach.swift:2:7 The out-of-order stepping behavior is confusing and unexpected to users. ISTM that the simplest way to fix this bug is to not attach debug locations to co...

Thanks, I seem to have gotten sub-registers to work. I can't seem to suppress the zero-extend sometimes. There is no need to explicitly zero extend bytes to words on this machine as all byte operations do that. I have also gotten some memory-to-memory to work. Bagel Evan Cheng wrote: > On Mar 14, 2008, at 10:17 AM, Bagel wrote: > >> I'm trying to write a backend for a

...eInstrs currently don't reliably record information about memory accesses. This is being addressed by MemOperands. However, currently there is a problem; the current code misses memory references in anonymous patterns, like this in x86: def : Pat<(zextloadi64i32 addr:$src), (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), x86_subreg_32bit)>; I can provide more details about what's going on here if anyone's interested. However, for people just interested in post-regalloc scheduling and VLIW packing and similar things, MemOperands aren't the only approach. A potentially...

Hi Andrew, Thanks for the feedback! On Fri, Mar 2, 2018 at 1:16 AM, Andrew Trick <atrick at apple.com> wrote: > > On Mar 1, 2018, at 9:22 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> > wrote: > > Hi all, > > At Sony we developed an LLVM based performance analysis tool named > llvm-mca. We > currently use it internally to statically measure the