search for: subreg_loreg

...(VMPYH (v2i16 (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$a))), subreg_hireg)), (v2i16 (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$b))), subreg_hireg)))), (v2i32 (VMPYH (v2i16 (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$a))), subreg_loreg)), (v2i16 (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$b))), subreg_loreg))))))) )>; Basically if we have a way to name a dag foo to be this: (EXTRACT_SUBREG (v4i16 (VSXTBH $X)), $Y) and bar to stand for this: (v2i32 (VMPYH (v2i16 (foo $X, $Z)), (v2i16 (foo $Y, $Z)))) the...

...uation. A3 = B0 ..... ..... B1 = A3 <--The copy C And if so, we check if we can merge the two ranges of B into a single range. However, this is not safe if A3 is a subreg define while A3 is not a subreg use. For instance, consider this code (part of a single block loop). MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, 2, // Post Inc. Load. Vreg7 is a 64bit reg. MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> // This is the A3 = B0 above. MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill&g...

Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation

...UBREG (v4i16 (VSXTBH (v4i8 IntRegs:$a))), > subreg_hireg)), > (v2i16 > (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$b))), > subreg_hireg)))), > (v2i32 > (VMPYH > (v2i16 > (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$a))), > subreg_loreg)), > (v2i16 > (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$b))), > subreg_loreg))))))) > )>; > > > Basically if we have a way to name a dag foo to be this: > (EXTRACT_SUBREG (v4i16 (VSXTBH $X)), $Y) > > and bar to stand for this: > (v2i32 (...

...ntRegs:%vreg61,%vreg56 %vreg62<def> = LDriuh_indexed %vreg56, 680; IntRegs:%vreg62,%vreg56 %R1<def> = TFRI 1431655766 ADJCALLSTACKDOWN 0, %R29<imp-def>, %R30<imp-def>, %R31<imp-use>, %R30<imp-use>, %R29<imp-use> %vreg304:subreg_loreg<def,read-undef> = ADDri_SUBr_V4 %vreg62, 5, %vreg61; DoubleRegs:%vreg304 IntRegs:%vreg62,%vreg61 %vreg519<def> = TFRI 3148; IntRegs:%vreg519 %vreg523<def> = TFRI64 15; DoubleRegs:%vreg523 %R0<def> = COPY %vreg304:subreg_loreg; DoubleRegs:%vreg304...

On Jul 8, 2012, at 3:42 PM, Sergei Larin <slarin at codeaurora.org> wrote: > ********** EXPANDING POST-RA PSEUDO INSTRS ********** > ********** Function: main > real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, > %D7<imp-def> > replaced by: %R15<def> = TFR %R4, %D7<imp-def> > > The R4 is a subreg of D2 double

Hello everyone, I am running into an obscure issue with ExpandPostRA. Does anyone recognizes the following: The pass replaces a real copy with a "transfer" instruction: ********** EXPANDING POST-RA PSEUDO INSTRS ********** ********** Function: main real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, %D7<imp-def> replaced by:

...ne($src1, $src2)", []>; def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh), (i32 32))), (i64 DoubleRegs:$srcLow))), (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg), (EXTRACT_SUBREG (i64 DoubleRegs:$srcLow), subreg_loreg)))>; ------------------------------------------------------------------ Thanks, Pranav Qualcomm Innovation Center, (QuIC) is a member of the Code Aurora Forum.

...B1 = A3 <--The copy C > > And if so, we check if we can merge the two ranges of B into a single range. > However, this is not safe if A3 is a subreg define while A3 is not a subreg > use. > For instance, consider this code (part of a single block loop). > > MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, > 2, // Post Inc. Load. Vreg7 is a 64bit reg. > MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> > // This is the A3 = B0 above. > MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:su...

...m<[1]>; def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; ... ...which could be accessed as double regs in pairs: // Aliases of the R* registers used to hold 64-bit int values (doubles). let SubRegIndices = [subreg_loreg, subreg_hireg] in { def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; So R2:R3 are subregs of D1. The...

..., "r2">, DwarfRegNum<[2]>; > def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; > ... > > ...which could be accessed as double regs in pairs: > > // Aliases of the R* registers used to hold 64-bit int values (doubles). > let SubRegIndices = [subreg_loreg, subreg_hireg] in { > def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; > def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; > def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; > > So R2:R3...

...Num<[2]>; > > def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; ... > > > > ...which could be accessed as double regs in pairs: > > > > // Aliases of the R* registers used to hold 64-bit int values > (doubles). > > let SubRegIndices = [subreg_loreg, subreg_hireg] in { > > def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; > > def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; > > def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; &gt...

Andy, Lang, Thanks for the suggestion. I have spent more time with it today, and I do see some strange things in liveness update. I am not at the actual cause yet, but here is what I got so far: I have the following live ranges when I start scheduling a region: R2 = [0B,48r:0)[352r,416r:5)... R3 = [0B,48r:0)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)...