Displaying 3 results from an estimated 3 matches for "subreg_extract".
2008 Sep 24
0
[LLVMdev] Multi-Instruction Patterns
...nship.
>
> I'm not seeing how this is "conceptually correct." It's a vector
> extract, not
> a subregister. It's just that we want to reuse the same register.
It is though. Sub-register is a machine specific concept. It means
vector_extract can be modeled as subreg_extract on this machine.
Nothing is wrong with thatt.
>
>
> Perhaps the answer is to add vector extract support to the
> coalescer, in
> the same way you added subregister support. I don't understand the
> nitty
> gritty of that, though.
I don't think that's a good...
2008 Sep 24
2
[LLVMdev] Multi-Instruction Patterns
On Wednesday 24 September 2008 02:10, Evan Cheng wrote:
> > I wrote a pattern that looks something like the above in form, but how
> > do I tell the selection DAG to prefer my pattern over another that
> > already exists. I can't easily just disable that other pattern
> > because
> > it generates Machine Instruction opcode enums that are assumed to be
> >
2008 Sep 24
1
[LLVMdev] Multi-Instruction Patterns
...39;m not seeing how this is "conceptually correct." It's a vector
> > extract, not
> > a subregister. It's just that we want to reuse the same register.
>
> It is though. Sub-register is a machine specific concept. It means
> vector_extract can be modeled as subreg_extract on this machine.
> Nothing is wrong with thatt.
I didn't mean to imply anything was "wrong." It just strikes me as kind of
strange, in a mind-warping kind of way. :)
> > Perhaps the answer is to add vector extract support to the
> > coalescer, in
> > the same...