Displaying 2 results from an estimated 2 matches for "subreg0".
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subregs
2007 Apr 23
0
[LLVMdev] Register based vector insert/extract
...;physreg, subreg#> pair should map to
another physreg (e.g. <RAX,1> -> AX).
The idea of this is that the register allocator allocates registers like
normal, but when it does the rewriting pass, when it replaces vregs with
pregs (e.g. r1024 with CX in this example), it rewrites r1024[subreg0]
with CL instead of CX. This would give us this code:
CX = X86_LOADi16 ...
DL = ADDi8 CL, 42
In your case, you'd define your vector register class with 4 subregs, one
for each piece.
Unfortunately, none of this exists yet :(. To handle truncates and
extends on X86, we currently e...
2007 Apr 23
2
[LLVMdev] Register based vector insert/extract
On Apr 23, 2007, at 1:43 PM, Christopher Lamb wrote:
> On Apr 23, 2007, at 1:17 PM, Christopher Lamb wrote:
>
>> On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote:
>>
>>> On Mon, 23 Apr 2007, Christopher Lamb wrote:
>>>> How can one let the back end know how to insert and extract
>>>> elements of
>>>> a vector through sub-register