search for: suboper

And another try for constant folding of Instructions for nvc0. Please Review this! Thanks, Tobias Klausmann Tobias Klausmann (4): nvc0/ir: clear subop when folding constant expressions nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant expressions nvc0/ir: Handle OP_BFIND when folding constant expressions nvc0/ir: Handle OP_POPCNT when folding constant expressions

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index 58092f4..93f7c2a 100644 ---

Yet another try for constant folding of Instructions for nvc0. Please Review this again! (Hopefully the last time ;-) ) Tobias Klausmann (4): nvc0/ir: clear subop when folding constant expressions nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant expressions nvc0/ir: Handle OP_BFIND when folding constant expressions nvc0/ir: Handle OP_POPCNT when folding constant

Tested with: MESA_EXTENSION_OVERRIDE=GL_ARB_gpu_shader5 ./shader_runner ../tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldReverse.shader_test -> green output, so this should be ok the test was not change though... On 29.05.2014 21:47, Ilia Mirkin wrote: > Can you verify that you tested how the HW handles this, as well as > exactly how you did it (i.e. how did you

Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> writes: > Some operations (e.g. OP_MUL/OP_MAD/OP_EXTBF might have a subop set. > After folding, make sure that it is cleared > > Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> > Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.1 10.2" <mesa-stable at

Some operations (e.g. OP_MUL/OP_MAD/OP_EXTBF might have a subop set. After folding, make sure that it is cleared Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

Can you verify that you tested how the HW handles this, as well as exactly how you did it (i.e. how did you modify the code + piglit test, what the results were, etc) On Thu, May 29, 2014 at 3:43 PM, Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> wrote: > Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> > --- >

V2: Handle the instruction right (shift after reverse) Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

Some operations (e.g. OP_MUL/OP_MAD/OP_EXTBF might have a subop set. After folding, make sure that it is cleared Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

Some operations (e.g. OP_MUL/OP_MAD/OP_EXTBF might have a subop set. After folding, make sure that it is cleared Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 1 + 1 file changed, 1 insertion(+) diff --git

On Mon, Jun 23, 2014 at 7:25 PM, Carl Worth <cworth at cworth.org> wrote: > Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> writes: >> Some operations (e.g. OP_MUL/OP_MAD/OP_EXTBF might have a subop set. >> After folding, make sure that it is cleared >> >> Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> >>

Hi, please review the following 4 patches: 1b1cfc6 nvc0/ir: Handle OP_BFIND when folding constant expressions d2d2727 nvc0/ir: Handle OP_POPCNT when folding constant expressions 86a1ee6 nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant expressions 84563bf nvc0/ir: clear subop when folding constant expressions src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 39

This is parallel to the pre-SM50 change which does this. Adjusts the shuffles / quadops to make the values correct relative to lane 0, and then splat the results to all lanes for the final move into the target register. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Entirely untested beyond compilation. Should check bin/tex-miplevel-selection textureGrad Cube

This is patch 2of2 of an eighth cut of the patch of the proposed XENMEM_claim_pages hypercall/subop, taking into account feedback from Jan and Keir and IanC and Matthew Daley. As requested by Jan, this is a separate post of the tools part of the patch. NOTE: This patch must be applied after the hypervisor part of the patchset or otherwise may break the build! v5->v8: - no change in this

I'm confused about how to specify DAG patterns for a given instruction Here is an example for my target class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode> : ALU_RR<subOp, asmstr, [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>; def ADD : ALU1_RR<0x0, "l.add", add>; The set operation simply creates a list. The add operation

i'm getting a Could not infer all types in pattern! error in my backend. it is happening on the following instruction: VGETITEM: (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32} VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)). how do i make it use appropriate types? in other words if it is f32 then use v4v32 and if it is i32 then use v4f32. i'm not sure even where to start? any help is appreciated.

Could you please get rid of the cosmetic changes (eg. the switch ones)? Because this doesn't really improve readability and in my opinion these changes should be eventually done in a separate patch. Other than that, this patch is : Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Yes, this probably won't work as is for atomic operations but the lowering pass is

On Tue, Dec 19, 2017 at 11:41 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > This is parallel to the pre-SM50 change which does this. Adjusts the > shuffles / quadops to make the values correct relative to lane 0, and > then splat the results to all lanes for the final move into the target > register. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> >

tgsi_default_instruction_memory / tgsi_build_instruction_memory were returning uninitialized memory for tgsi_instruction_memory.Texture and tgsi_instruction_memory.Format. Note 0 means not set, and thus is a correct default initializer for these. Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory") Cc: Nicolai Hähnle <nicolai.haehnle at amd.com>

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with its operands being subnodes. > >