Displaying 3 results from an estimated 3 matches for "subopcod".
Did you mean:
subopcode
2017 Sep 25
1
TableGen questions.
...bly not correct due to name mangling).
class IO_MultSrc<bits<2> op0Type, RegisterClass Src0RC> {
dag insDefault = !if(!eq(op0Type, 0b01),
(ins SpecialReg:$dst, Src0RC:$a),
(ins Src0RC:$a));
...
}
multiclass MultSrc1Spec<bits<5> subOpcode, bits<2> op0t, string opcodeStr,
RegisterClass RegType> {
def _allspecial:
MultSrcOneDestInst<subOpcode, op0t, 0b00,
IO_MultSrc<op0t, SpecialReg>.outsDefault,
IO_MultSrc<op0t, SpecialReg>.insDefault>;
...
}...
2009 Jul 10
2
[LLVMdev] Help: Instruction Pattern Matching question
...pectation. Could anybody please help?
Here is the example:
I want to emit instruction for adding 2 different kind of oprands. Basically i want to mix register types when I define the instruction for add,sub etc
I define the instruction TargetInstruction.td as follows:
class MyInst
<opcode op,subopcode subop,
dag outs, dag ins, string asmstr,list<dag> pattern>
Instruction
{
let Namespce = "MyNameSpace";
MyOpCode myop = op;
MySubOpcode mysubop = subop;
dag OutOprandList = outs;
dag InOprandList = ins;
let ASMString = asmstr;
let Pattern = pattern;
}
d...
2017 Sep 26
0
TableGen questions.
>
> On 9/25/2017 6:03 PM, Shane Ryoo via llvm-dev wrote:
> > MultSrcOneDestInst<subOpcode, op0t, 0b00,
> > IO_MultSrc<op0t, SpecialReg>.outsDefault,
> > IO_MultSrc<op0t, SpecialReg>.insDefault>;
> I suspect that the use of IO_MultSrc here is the culprit. TableGen has
> some limitations here, when it co...