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...9;t spend time to figure out why), following which CMake produced a nice working Visual Studio 2008 solution file. I opened this up in VS 2008 Express and everything seems to build properly except for the following errors: 1>c:\llvm\utils\tablegen\TGParser.h(69) : warning C4099: 'llvm::SubClassReference' : type name first seen using 'struct' now seen using 'class' 1> c:\llvm\utils\tablegen\TGParser.h(26) : see declaration of 'llvm::SubClassReference' 1>c:\llvm\utils\tablegen\Record.h(38) : warning C4099: 'llvm::Init' : type name first seen using...

On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > > Currently, we rely on switch tables to transform between formats. However, > we would like to have a different mechanism to represent these relationships > instead of switch tables. I am thinking of modeling these relations in > HexagonInstrInfo.td file and use TableGen to generate a table with

...gon class. This eventually becomes part of the instruction definition (record). bool TGParser::ParseDefm(MultiClass *CurMultiClass) { ... if (InheritFromClass) { // Process all the classes to inherit as if they were part of a // regular 'def' and inherit all record values. SubClassReference SubClass = ParseSubClassReference(0, false); while (1) { // Check for error. if (SubClass.Rec == 0) return true; // Get the expanded definition prototypes and teach them about // the record values the current class to inherit has for (unsigned i = 0, e = NewRecDef...

Hi, I'm looking for some suggestions on a problem related to the Hexagon backend. Hexagon architecture allows instructions in various formats. For example, we have 3 variations of the add instruction as defined below: ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 = add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is true ADDrr_np :