search for: subccri

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2010 Feb 08
2
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
...ors according to CFG: BB#314 %reg1731<def> = SETHIi 1856 %reg1732<def> = ORri %G0, 1 %reg1733<def> = SLLrr %reg1732, %reg1729 %reg1734<def> = ORri %reg1731, 1 %reg1735<def> = ANDrr %reg1733, %reg1734 %reg1736<def> = SUBCCri %reg1735, 0, %ICC<imp-def> BCOND <BB#3>, 9, %ICC<imp-use> BA <BB#53> Successors according to CFG: BB#3 BB#53 BB#3: derived from LLVM BB %bb1 Predecessors according to CFG: BB#315 %reg1740<def> = ANDri %reg1067, 255 %reg1741<d...
2009 Dec 11
2
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
Hi, Chris > That is target independent code, so you should not put sparc specific changes there.  It sounds like one of the sparc-specific target hooks is wrong. Since sparc does not provide any hooks for operation of branches (e.g. AnalyzeBranch and friends) it might be possible that generic codegen code is broken in absence of these hooks. -- With best regards, Anton Korobeynikov Faculty
2010 Feb 08
0
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
...%L5<def> = SETHIi 1856 > %L6<def> = ORri %G0, 1 > %L3<def> = SLLrr %L6<kill>, %L3<kill> > %L5<def> = ORri %L5<kill>, 1 > %L3<def> = ANDrr %L3<kill>, %L5<kill> > %L3<def,dead> = SUBCCri %L3<kill>, 0, %ICC<imp-def> > BCOND <BB#8>, 9, %ICC<imp-use,kill> > NOP > BA <BB#68> > NOP > > which leads MachineBasicBlock::isOnlyReachableByFallthrough() to > return TRUE for BB#8, since the final NOP is not a '...
2013 Mar 24
5
[LLVMdev] Types in TableGen instruction selection patterns
...type inference errors when multiple types are added to a register class. In the output pattern, it is no longer necessary to duplicate the register classes or types of register operands. For immediate operands, the 'imm' tag is still required: def : Pat<(subc i32:$b, simm13:$val), (SUBCCri $b, imm:$val)>; I would like for the old register class notation to go away eventually. /jakob
2010 Feb 09
3
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
...ef> = SETHIi 1856 >> %L6<def> = ORri %G0, 1 >> %L3<def> = SLLrr %L6<kill>, %L3<kill> >> %L5<def> = ORri %L5<kill>, 1 >> %L3<def> = ANDrr %L3<kill>, %L5<kill> >> %L3<def,dead> = SUBCCri %L3<kill>, 0, %ICC<imp-def> >> BCOND <BB#8>, 9, %ICC<imp-use,kill> >> NOP >> BA <BB#68> >> NOP >> >> which leads MachineBasicBlock::isOnlyReachableByFallthrough() to return TRUE for BB#8, since the final NOP...
2013 Apr 20
0
[LLVMdev] Types in TableGen instruction selection patterns
...ltiple types are added to a register class. > > In the output pattern, it is no longer necessary to duplicate the register classes or types of register operands. > > For immediate operands, the 'imm' tag is still required: > > def : Pat<(subc i32:$b, simm13:$val), (SUBCCri $b, imm:$val)>; > > > I would like for the old register class notation to go away eventually. > Hi Jakob, I'm going through the R600 target and converting all the patterns to the new syntax, and I've come across a pattern that I'm unable to convert: class BitConvert...
2010 Feb 14
0
[LLVMdev] sparc status llvm 2.7?
...>>> %L6<def> = ORri %G0, 1 >>> %L3<def> = SLLrr %L6<kill>, %L3<kill> >>> %L5<def> = ORri %L5<kill>, 1 >>> %L3<def> = ANDrr %L3<kill>, %L5<kill> >>> %L3<def,dead> = SUBCCri %L3<kill>, 0, %ICC<imp-def> >>> BCOND <BB#8>, 9, %ICC<imp-use,kill> >>> NOP >>> BA <BB#68> >>> NOP >>> >>> which leads MachineBasicBlock::isOnlyReachableByFallthrough() to return TRUE for BB#...