search for: sub_xmm

Displaying 8 results from an estimated 8 matches for "sub_xmm".

2011 Aug 25
2
[LLVMdev] AVX spill alignment
Hey guys, Are spills/reloads of AVX registers using aligned stores/loads? I can't seem to find the code that aligns the stack slots to 32-bytes. Could someone point me in the right direction? Thanks, Cameron -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110825/b5724dec/attachment.html>
2011 Sep 01
0
[LLVMdev] AVX spill alignment
...e in the right direction? The register class has 256-bit spill alignment: def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 256, (sequence "YMM%u", 0, 15)> { let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)]; } /jakob
2011 Sep 01
1
[LLVMdev] AVX spill alignment
...> > The register class has 256-bit spill alignment: > > def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], > 256, (sequence "YMM%u", 0, 15)> { > let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)]; > } > > /jakob > > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110901/3403477c/attachment.html>
2012 Jan 09
3
[LLVMdev] Calling conventions for YMM registers on AVX
On Jan 9, 2012, at 10:00 AM, Jakob Stoklund Olesen wrote: > > On Jan 8, 2012, at 11:18 PM, Demikhovsky, Elena wrote: > >> I'll explain what we see in the code. >> 1. The caller saves XMM registers across the call if needed (according to DEFS definition). >> YMMs are not in the set, so caller does not take care. > > This is not how the register allocator
2012 Jan 10
0
[LLVMdev] Calling conventions for YMM registers on AVX
...ster<"xmm13b">, DwarfRegNum<[30, -2, -2]>; def XMM14b: Register<"xmm14b">, DwarfRegNum<[31, -2, -2]>; def XMM15b: Register<"xmm15b">, DwarfRegNum<[32, -2, -2]>; // YMM Registers, used by AVX instructions let SubRegIndices = [sub_xmm, sub_xmmb] in { def YMM0: RegisterWithSubRegs<"ymm0", [XMM0, XMM0b]>, DwarfRegNum<[17, 21, 21]>; def YMM1: RegisterWithSubRegs<"ymm1", [XMM1, XMM1b]>, DwarfRegNum<[18, 22, 22]>; def YMM2: RegisterWithSubRegs<"ymm2", [XMM2, XMM2b]>, D...
2017 Aug 06
2
VBROADCAST Implementation Issues
...;>>>>>>> for v16f32 it is defined as; >>>>>>>>>> : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))), >>>>>>>>>> (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), >>>>>>>>>> sub_xmm))>; >>>>>>>>>> which is similar to mine. >>>>>>>>>> Why its not working then? >>>>>>>>>> >>>>>>>>>> On Sun, Aug 6, 2017 at 1:45 AM, Craig Topper < >>>>>>&g...
2017 Aug 07
2
VBROADCAST Implementation Issues
...;> for v16f32 it is defined as; >>>>>>>>>>>> : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))), >>>>>>>>>>>> (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), >>>>>>>>>>>> sub_xmm))>; >>>>>>>>>>>> which is similar to mine. >>>>>>>>>>>> Why its not working then? >>>>>>>>>>>> >>>>>>>>>>>> On Sun, Aug 6, 2017 at 1:45 AM, Craig Topper...
2017 Aug 07
3
VBROADCAST Implementation Issues
...gt;>>>>>>>>>>>> : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))), >>>>>>>>>>>>>>>> (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 >>>>>>>>>>>>>>>> VR512:$src), sub_xmm))>; >>>>>>>>>>>>>>>> which is similar to mine. >>>>>>>>>>>>>>>> Why its not working then? >>>>>>>>>>>>>>>> >>>>>>>>>>>&...