Displaying 1 result from an estimated 1 matches for "sub_word".
2013 Jan 11
2
[LLVMdev] Sub-Register Allocation
...s
move.w #0, d0
move.b 4(a7), d0
would work just as well.
If however, I load the 32 bit portion of the register with 0, truncate it
to 16bits, and then copy in the 8 bit portion, I get what I expect.
def : Pat<(i16 (zextloadi8 addr:$src)),
(INSERT_SUBREG (EXTRACT_SUBREG (MOVQ32 0), sub_word),
(MOV8md addr:$src),
sub_byte)>;
zext_i8_to_i16_simple PROC ; @zext_i8_to_i16_simple
; BB#0:
moveq #0, d0
move.b 4(a7), d0
rts
I'm building off of the llvm 3.2 release, if it matters. I'm mostly...