Displaying 7 results from an estimated 7 matches for "sub_hi".
2013 Oct 08
2
[LLVMdev] Subregister liveness tracking
...Hi,
>
> I have a question about the way sub-registers are spilled and restored
> that is related to the changes I made in r192119.
>
> Suppose I have the following piece of code with four
> instructions. %vreg0 and %vreg1 consist of two sub-registers indexed
> by sub_lo and sub_hi.
>
> instr0 %vreg0<def>
> instr1 %vreg1:sub_lo<def,read-undef>
> instr2 %vreg0<use>
> instr3 %vreg1:sub_hi<def>
>
> If register allocator decides to insert spill and restore instructions
> for %vreg0, will it spill the whole register that includes
&...
2013 Oct 08
0
[LLVMdev] Subregister liveness tracking
...Hi,
>
> I have a question about the way sub-registers are spilled and restored
> that is related to the changes I made in r192119.
>
> Suppose I have the following piece of code with four
> instructions. %vreg0 and %vreg1 consist of two sub-registers indexed by
> sub_lo and sub_hi.
>
> instr0 %vreg0<def>
> instr1 %vreg1:sub_lo<def,read-undef>
> instr2 %vreg0<use>
> instr3 %vreg1:sub_hi<def>
>
> If register allocator decides to insert spill and restore instructions
> for %vreg0, will it spill the whole register that includes...
2013 Oct 09
4
[LLVMdev] Subregister liveness tracking
...Hi,
>>
>> I have a question about the way sub-registers are spilled and restored that is related to the changes I made in r192119.
>>
>> Suppose I have the following piece of code with four instructions. %vreg0 and %vreg1 consist of two sub-registers indexed by sub_lo and sub_hi.
>>
>> instr0 %vreg0<def>
>> instr1 %vreg1:sub_lo<def,read-undef>
>> instr2 %vreg0<use>
>> instr3 %vreg1:sub_hi<def>
>>
>> If register allocator decides to insert spill and restore instructions for %vreg0, will it spill the whole r...
2013 Oct 07
1
[LLVMdev] Subregister liveness tracking
I've been working on patches to improve subregister liveness tracking on
llvm and I wanted to inform the llvm community about the overal
design/motivation for them. I will send the patches to llvm-commits
later today.
Greetings
Matthias Braun
Subregisters in llvm
====================
Some targets can access registers in different ways resulting in wider or
narrower accesses. For
2018 Nov 10
3
[RFC] Tablegen-erated GlobalISel Combine Rules
...up needing a lot of pseudo-nodes like EXTRACT_SUBREG whereas these are natural parts of the MIR syntax. For example:
(set $d, (EXTRACT_SUBREG (MYTGT_ADD $A, $B), sub_lo))
compared to:
%d:sub_lo = MYTGT_ADD %A, %B
and:
(set $d, (REG_SEQUENCE GPR32, (MYTGT_ADD $A, $B), sub_lo, (MYTGT_ADD $C, $D), sub_hi))
compared to:
%d:sub_lo = MYTGT_ADD %A, %B
%d:sub_hi = MYTGT_ADD %C, %D
Along the same lines, I also think that the integrated debug-info is only really practical in MIR. It's possible to shoe-horn DILocation in using a pseudo-node like so:
(set $d, (add (mul $a, $b):$mul, $c):$add -&g...
2018 Nov 12
3
[RFC] Tablegen-erated GlobalISel Combine Rules
...RACT_SUBREG whereas these are natural parts of the MIR syntax. For example:
>> (set $d, (EXTRACT_SUBREG (MYTGT_ADD $A, $B), sub_lo))
>> compared to:
>> %d:sub_lo = MYTGT_ADD %A, %B
>> and:
>> (set $d, (REG_SEQUENCE GPR32, (MYTGT_ADD $A, $B), sub_lo, (MYTGT_ADD $C, $D), sub_hi))
>> compared to:
>> %d:sub_lo = MYTGT_ADD %A, %B
>> %d:sub_hi = MYTGT_ADD %C, %D
>
> How about:
>
> (MYTGT_ADD (sub_lo $d), $A, $B),
> (MYTGT_ADD (sub_hi $d), $C, $D),
>
> That seems acceptable to me.
That looks good to me too.
>> Along the same...
2018 Nov 09
5
[RFC] Tablegen-erated GlobalISel Combine Rules
Hi All,
I've been working on the GlobalISel combiner recently and I'd like to share the plan for how Combine Rules will be defined in GlobalISel and solicit feedback on it.
This email ended up rather long so:
TL;DR: We're planning to define GlobalISel Combine Rules using MIR syntax with a few bits glued on to interface with the algorithm and escape into C++ when we need to.