Displaying 6 results from an estimated 6 matches for "sub_8bit".
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sub_32bit
2018 Aug 06
2
Lowering ISD::TRUNCATE
I'm working on defining the instructions and implementing the lowering
code for a Z80 backend. For now, the backend supports only the native
CPU-supported datatypes, which are 8 and 16 bits wide (i.e. no 32 bit
long, float, ... yet).
So far, a lot of the simple stuff like immediate loads and return values
is very straightforward, but now I got stuck with ISD::TRUNCATE, as in:
2013 May 16
1
[LLVMdev] Combining physical registers
...d by getSubRegIndexLaneMask() above can only be
/// used to determine if sub-registers overlap - they can't be used to
/// determine if a set of sub-registers completely cover another
/// sub-register.
///
/// The X86 general purpose registers have two lanes corresponding to the
/// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
/// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
/// sub_32bit sub-register.
///
/// On the other hand, the ARM NEON lanes fully cover their registers: The
/// dsub_0 sub-register is com...
2017 Aug 02
3
[InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
...so we still need to check "AND32ri8 %vreg0<tied0>,
31" is colder than "AND32ri %vreg0<tied0>, 1792".
All these efforts are just handling a specific pattern, and if the
pattern changes a little bit, they won't work.
BB_i:
%vreg9<def> = COPY %vreg0:sub_8bit; GR8:%vreg9 GR32:%vreg0
%vreg1<def> = MOVZX32rr8 %vreg9<kill>; GR32:%vreg1 GR8:%vreg9
%vreg10<def,tied1> = AND32ri %vreg0<tied0>, 1792,
%EFLAGS<imp-def,dead>; GR32:%vreg10,%vreg0
...
BB_j:
%vreg4<def,tied1> = AND32ri8 %vreg0<tied0>,...
2013 May 16
2
[LLVMdev] Combining physical registers
The function TII::canCombineSubRegIndices has been gone for a while now,
and I was wondering if there is a target-independent way of determining
if a certain set of physical registers "adds up" to a larger register.
For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1
are D0.
The context here is an attempt to coalesce multiple loads/stores into
fewer loads/stores
2017 Aug 02
3
[InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
...vreg0<tied0>,
>> 31" is colder than "AND32ri %vreg0<tied0>, 1792".
>> All these efforts are just handling a specific pattern, and if the
>> pattern changes a little bit, they won't work.
>> BB_i:
>> %vreg9<def> = COPY %vreg0:sub_8bit; GR8:%vreg9 GR32:%vreg0
>> %vreg1<def> = MOVZX32rr8 %vreg9<kill>; GR32:%vreg1 GR8:%vreg9
>> %vreg10<def,tied1> = AND32ri %vreg0<tied0>, 1792,
>> %EFLAGS<imp-def,dead>; GR32:%vreg10,%vreg0
>> ...
>> BB_j:
>> %vreg...
2017 Aug 02
2
[InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
...check "AND32ri8 %vreg0<tied0>,
> 31" is colder than "AND32ri %vreg0<tied0>, 1792".
> All these efforts are just handling a specific pattern, and if the
> pattern changes a little bit, they won't work.
> BB_i:
> %vreg9<def> = COPY %vreg0:sub_8bit; GR8:%vreg9 GR32:%vreg0
> %vreg1<def> = MOVZX32rr8 %vreg9<kill>; GR32:%vreg1 GR8:%vreg9
> %vreg10<def,tied1> = AND32ri %vreg0<tied0>, 1792,
> %EFLAGS<imp-def,dead>; GR32:%vreg10,%vreg0
> ...
> BB_j:
> %vreg4<def,tied1> = AND32r...