Displaying 5 results from an estimated 5 matches for "sub_16bit".
2010 Nov 08
2
[LLVMdev] [LLVMDev] Register Allocation and copy instructions
..., fixed, at location [SP+8]
fi#-1: size=2, align=8, fixed, at location [SP+4]
Function Live Outs: %AX
BB#0: derived from LLVM BB %entry
%reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0;
mem:LD2[FixedStack-2] GR32:%reg16390
%reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385
GR32:%reg16390
%reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0;
mem:LD2[FixedStack-1] GR32:%reg16391
%reg16384<def> = COPY %reg16391:sub_16bit<kill>; GR16:%reg16384
GR32:%reg16391
Successors according to CFG: BB#1
......
2010 Nov 08
0
[LLVMdev] [LLVMDev] Register Allocation and copy instructions
...ecute %reg16385<def> = COPY %reg16390. Furthermore, how should I handle this case.
> BB#0: derived from LLVM BB %entry
> %reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390
> %reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390
> %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391
> %reg16384<def> = COPY %reg16391:sub_16bit<kill>; GR16:%reg16384 GR32:%reg16391
> Successors according to...
2013 May 16
1
[LLVMdev] Combining physical registers
...to determine if sub-registers overlap - they can't be used to
/// determine if a set of sub-registers completely cover another
/// sub-register.
///
/// The X86 general purpose registers have two lanes corresponding to the
/// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
/// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
/// sub_32bit sub-register.
///
/// On the other hand, the ARM NEON lanes fully cover their registers: The
/// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
/// This i...
2013 May 16
2
[LLVMdev] Combining physical registers
The function TII::canCombineSubRegIndices has been gone for a while now,
and I was wondering if there is a target-independent way of determining
if a certain set of physical registers "adds up" to a larger register.
For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1
are D0.
The context here is an attempt to coalesce multiple loads/stores into
fewer loads/stores
2016 Sep 29
3
Reg units for unaddressable register parts?
On 9/28/2016 7:30 PM, Quentin Colombet wrote:
> Out of curiosity, could describe why this is useful to have such precision in the liveness tracking?
RDF is meant to allow optimizations across the whole function. As a
result, registers may change between basic blocks, and there is code to
recalculate it. Accuracy is required to avoid unnecessary block live-ins.
For example, calculate live-ins