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sub_32bit
2009 Feb 13
3
[LLVMdev] 16bit loads being promoted to 32bit?
...oad and then the lower 16 bits are being sign
extended away with a shl 16 followed by a shr 16.
The problem with this is that
1) I'm limited to 32bit aligned loads and llvm is assuming a
16bit/8bit alignment
2) I have special functions that I need to be called when a load
of sub32bit data type occurs which handles the alignment constraints and
then does the shifting and masking of the data
So my questions are:
What bits do I need to flip to stop this optimization from occurring?
What do I need to set to correctly get the loads/stores generated if not
setting the datalayou...