search for: sub16rr

...def> JCC mbb<if.end7,0xa244cb8>, 5, %SRW<imp-use> Successors according to CFG: 0xa244c6c (#2) 0xa244cb8 (#3) if.then5: 0xa244c6c, LLVM BB @0xa1e93c0, ID#2: Live Ins: %R15W %R15B Predecessors according to CFG: 0xa244c20 (#1) %R12W<def> = MOV16ri 10 %R12W<def> = SUB16rr %R12W, %R15W<kill>, %SRW<imp-def> %R15W<def> = MOV16rr %R12W<kill> RET %R15W<imp-use,kill> if.end7: 0xa244cb8, LLVM BB @0xa1f09c0, ID#3: Live Ins: %R15W %R15B Predecessors according to CFG: 0xa244c20 (#1) %R15W<def> = ADD16ri %R15W, 18, %SRW<imp-def&gt...

...CALLi <ga:@clock_get_ticks>, <regmask>, %SP<imp-use>, %SP<imp-def>, %A<imp-def>, ... ADJCALLSTACKUP 0, 0, %SP<imp-def>, %EX<imp-def>, %SP<imp-use> %vreg57<def> = COPY %A<kill>; GR16:%vreg57 %vreg58<def> = SUB16rr %vreg57, %vreg18<kill>, %EX<imp-def>; GR16:%vreg58,%vreg57 GEXR16:%vreg18 %vreg59<def> = ADD16rm %vreg58<kill>, <fi#1>, 16, %EX<imp-def>; mem:LD1[%sunkaddr21](align=8)(tbaa=!"int") GR16:%vreg59,%vreg58 MOV16mr <fi#1>, 16, %vreg59;...

Greetings, LLVM devs, For the past few weeks, I have been putting together a 6502 backend for LLVM. The 6502 and its derivatives, of course, have powered countless microcomputers, game consoles and arcade machines over the past 40 years. The backend is just an experimental hobby project right now. The code is available here: <https://github.com/beholdnec/llvm-m6502>. This branch introduces