search for: stwcx

Hi, I want to take an intrinsic function, and get the PowerPC back end to emit: loop: lwarx ... add ... stwcx. ... bne- loop I can successfully emit: lwarx ... add ... stwcx. ... How do I emit a label and a branch instruction? Thanks, Brent

Hi all, I'm trying to figure out how to add the instructions required for llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch attached) but the other two (CMP_UNRESw and STWCX) require multiple instructions: let Defs = [CR0] in { def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>;...

...succeeded + * in getting the lock if the return value is 0. + */ +static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock) +{ + unsigned long tmp, token; + + token = LOCK_TOKEN; + __asm__ __volatile__( +"1: " PPC_LWARX(%0,0,%2,1) "\n\ + cmpwi 0,%0,0\n\ + bne- 2f\n\ + stwcx. %1,0,%2\n\ + bne- 1b\n" + PPC_ACQUIRE_BARRIER +"2:" + : "=&r" (tmp) + : "r" (token), "r" (&lock->slock) + : "cr0", "memory"); + + return tmp; +} + +static inline int arch_spin_trylock(arch_spinlock_t *lock) +{ + return _...

...atomic_t *a = &lock->val; + u32 val; + +again: + asm volatile( +"1:\t" PPC_LWARX(%0,0,%1,1) " # queued_spin_lock \n" + : "=&r" (val) + : "r" (&a->counter) + : "memory"); + + if (likely(val == 0)) { + asm_volatile_goto( + " stwcx. %0,0,%1 \n" + " bne- %l[again] \n" + "\t" PPC_ACQUIRE_BARRIER " \n" + : + : "r"(_Q_LOCKED_VAL), "r" (&a->counter) + : "cr0", "memory" + : again ); return; - - queued_spin_lock_slowpath(lock, va...

...atomic_t *a = &lock->val; + u32 val; + +again: + asm volatile( +"1:\t" PPC_LWARX(%0,0,%1,1) " # queued_spin_lock \n" + : "=&r" (val) + : "r" (&a->counter) + : "memory"); + + if (likely(val == 0)) { + asm_volatile_goto( + " stwcx. %0,0,%1 \n" + " bne- %l[again] \n" + "\t" PPC_ACQUIRE_BARRIER " \n" + : + : "r"(_Q_LOCKED_VAL), "r" (&a->counter) + : "cr0", "memory" + : again ); return; - - queued_spin_lock_slowpath(lock, va...

Hello, Gary > I'm trying to figure out how to add the instructions required for > llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch > attached) Applied, thanks! > but the other two (CMP_UNRESw and STWCX) require multiple > instructions: > > let Defs = [CR0] in { > def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), > "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", > [(PPCstcx GPRC:$rS, xoa...

...gt; > + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) > + .addReg(ptrA).addReg(ptrB); > + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) > + .addReg(incr).addReg(dest); > + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) > + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); > > The second instruction defines R0 and the 3rd reads R0 which is > enough to tell the register allocator what to do. > > I do have a question, must it use R0? If it's not fixed, it's > probably better to create...

...places, so it shouldn't be a huge change. I need to generate labels in PPCTargetLowering::LowerAtomicCMP_SWAP however: how do I do that? FWIW the code it needs to emit is: ; inputs: ptr, oldval, newval loop: lwarx $tmp, 0, $ptr cmpw $oldval, $tmp bne- exit stwcx. $newval, 0, $ptr bne- loop exit: ... Cheers, Gary -- http://gbenson.net/

...xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; + def ATOMIC_SWAP_I32 : Pseudo< + (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), + "${:comment} ATOMIC_SWAP_I32 PSEUDO!", + [(set GPRC:$dst, (PPCatomic_swap xoaddr:$ptr, GPRC:$new))]>; + } +} -let Defs = [CR0] in { -def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), - "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LWARX : XForm_1<31,...

...xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; + def ATOMIC_SWAP_I32 : Pseudo< + (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), + "${:comment} ATOMIC_SWAP_I32 PSEUDO!", + [(set GPRC:$dst, (PPCatomic_swap xoaddr:$ptr, GPRC:$new))]>; + } +} -let Defs = [CR0] in { -def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), - "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LWARX : XForm_1<31,...

...uildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) >> + .addReg(ptrA).addReg(ptrB); >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) >> + .addReg(incr).addReg(dest); >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) >> + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); >> >> The second instruction defines R0 and the 3rd reads R0 which is >> enough to tell the register allocator what to do. >> >> I do have a question, must it use R0? If it's not fixed, it's >>...

...change. > I need to generate labels in PPCTargetLowering::LowerAtomicCMP_SWAP > however: how do I do that? FWIW the code it needs to emit is: > > ; inputs: ptr, oldval, newval > loop: > lwarx $tmp, 0, $ptr > cmpw $oldval, $tmp > bne- exit > stwcx. $newval, 0, $ptr > bne- loop > exit: > ... > > > Cheers, > Gary > > -- > http://gbenson.net/ > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://...

...et(is64bit ? PPC::LDARX : PPC::LWARX), dest) > >> + .addReg(ptrA).addReg(ptrB); > >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) > >> + .addReg(incr).addReg(dest); > >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) > >> + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); > >> > >> The second instruction defines R0 and the 3rd reads R0 which is > >> enough to tell the register allocator what to do. > >> > >> I do have a question, must it use R0? If it'...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; + def ATOMIC_SWAP_I32 : Pseudo< + (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), + "${:comment} ATOMIC_SWAP_I32 PSEUDO!", + [(set GPRC:$dst, (PPCatomic_swap xoaddr:$ptr, GPRC:$new))]>; + } +} -let Defs = [CR0] in { -def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), - "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LWARX : XForm_1<31,...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

...xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; + def ATOMIC_SWAP_I32 : Pseudo< + (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), + "${:comment} ATOMIC_SWAP_I32 PSEUDO!", + [(set GPRC:$dst, (PPCatomic_swap xoaddr:$ptr, GPRC:$new))]>; + } +} -let Defs = [CR0] in { -def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), - "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LWARX : XForm_1<31,...

v2 is updated to account for feedback from Will, Peter, and Waiman (thank you), and trims off a couple of RFC and unrelated patches. Thanks, Nick Nicholas Piggin (6): powerpc/powernv: must include hvcall.h to get PAPR defines powerpc/pseries: move some PAPR paravirt functions to their own file powerpc: move spinlock implementation to simple_spinlock powerpc/64s: implement queued