Displaying 20 results from an estimated 20 matches for "stur".
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2020 Jun 22
3
Hardware ASan Generating Unknown Instruction
...3 00 d1 sub x2, x29, #4
2d4e8: e9 03 08 aa mov x9, x8
2d4ec: df 64 ff 97 bl #-158852
<__hwasan_check_x2_18_short>
2d4f0: ea 03 1f 2a mov w10, wzr
2d4f4: aa c3 1f b8 stur w10, [x29, #-4]
2d4f8: a2 23 00 d1 sub x2, x29, #8
2d4fc: e9 03 08 aa mov x9, x8
2d500: da 64 ff 97 bl #-158872
<__hwasan_check_x2_18_short>
2d504: a0 83 1f b8 stur w0, [x29, #-8]...
2020 Jun 22
3
Hardware ASan Generating Unknown Instruction
...#4
>> 2d4e8: e9 03 08 aa mov x9, x8
>> 2d4ec: df 64 ff 97 bl #-158852
>> <__hwasan_check_x2_18_short>
>> 2d4f0: ea 03 1f 2a mov w10, wzr
>> 2d4f4: aa c3 1f b8 stur w10, [x29, #-4]
>> 2d4f8: a2 23 00 d1 sub x2, x29, #8
>> 2d4fc: e9 03 08 aa mov x9, x8
>> 2d500: da 64 ff 97 bl #-158872
>> <__hwasan_check_x2_18_short>
>> 2d504: a0 83 1f b8...
2020 Jun 22
2
Hardware ASan Generating Unknown Instruction
...mov x9, x8
> >>> 2d4ec: df 64 ff 97 bl #-158852
> >>> <__hwasan_check_x2_18_short>
> >>> 2d4f0: ea 03 1f 2a mov w10, wzr
> >>> 2d4f4: aa c3 1f b8 stur w10, [x29, #-4]
> >>> 2d4f8: a2 23 00 d1 sub x2, x29, #8
> >>> 2d4fc: e9 03 08 aa mov x9, x8
> >>> 2d500: da 64 ff 97 bl #-158872
> >>> <__hwasan_check_x2_18_short&...
2017 May 11
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...eg2/mpeg2dec/mpeg2decode (46%): Function
> Reference_IDCT: Probably due to creating all constants in the entry BB +
> spilling floating point data through an X register:
>
> FastISel:
> fadd d0, d1, d0
> str d0, [sp,#528]
> GlobalISel:
> fadd d0, d1, d0
> fmov x9, d0
> stur x9, [x29,#-48]
>
>
> Good finding, I forgot to do stores in my previous fix. I’ll do them
> shortly.
>
>
> Should be fixed by r302679
>
>
> Thanks Quentin,
>
> That reduces the slow-down when enabling globalisel at -O0 from 13% (on
> r302453) to 9.5% (on r302...
2017 May 12
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...eg2/mpeg2dec/mpeg2decode (46%): Function
> Reference_IDCT: Probably due to creating all constants in the entry BB +
> spilling floating point data through an X register:
>
> FastISel:
> fadd d0, d1, d0
> str d0, [sp,#528]
> GlobalISel:
> fadd d0, d1, d0
> fmov x9, d0
> stur x9, [x29,#-48]
>
>
> Good finding, I forgot to do stores in my previous fix. I’ll do them
> shortly.
>
>
> Should be fixed by r302679
>
>
> Thanks Quentin,
>
> That reduces the slow-down when enabling globalisel at -O0 from 13% (on
> r302453) to 9.5% (on r302...
2017 May 10
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...es.
>> Same issue causes MultiSource/Applications/sqlite3/sqlite3 (71%).
>> Same issue causes MultiSource/Applications/lua/lua (46%).
>> SingleSource/Benchmarks/Misc/flops-2 (75%): Poor lowering of fneg:
>> FastISel:
>> ldur d0, [x29,#-16]
>> fneg d0, d0
>> stur d0, [x29,#-16]
>> GlobalISel:
>> ldur d0, [x29,#-64]
>> orr x8, xzr, #0x8000000000000000
>> fmov d1, x8
>> fsub d0, d1, d0
>> fmov x8, d0
>> stur x8, [x29,#-64]
>> MultiSource/Benchmarks/Prolangs-C++/city/city (74%): a call to memcpy for copying 4 byt...
2017 May 12
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...ating all constants in the entry BB +
> >> spilling floating point data through an X register:
> >>
> >> FastISel:
> >> fadd d0, d1, d0
> >> str d0, [sp,#528]
> >> GlobalISel:
> >> fadd d0, d1, d0
> >> fmov x9, d0
> >> stur x9, [x29,#-48]
> >>
> >>
> >> Good finding, I forgot to do stores in my previous fix. I’ll do them
> >> shortly.
> >>
> >>
> >> Should be fixed by r302679
> >>
> >>
> >> Thanks Quentin,
> >>
> >...
2017 May 09
4
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...as cascaded-sequence-of-conditional-branches.
Same issue causes MultiSource/Applications/sqlite3/sqlite3 (71%).
Same issue causes MultiSource/Applications/lua/lua (46%).
* SingleSource/Benchmarks/Misc/flops-2 (75%): Poor lowering of fneg:
* FastISel:
ldur d0, [x29,#-16]
fneg d0, d0
stur d0, [x29,#-16]
* GlobalISel:
ldur d0, [x29,#-64]
orr x8, xzr, #0x8000000000000000
fmov d1, x8
fsub d0, d1, d0
fmov x8, d0
stur x8, [x29,#-64]
* MultiSource/Benchmarks/Prolangs-C++/city/city (74%): a call to memcpy for copying 4 bytes is present with GlobalISel that isn't presen...
2017 May 09
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...rce/Applications/sqlite3/sqlite3 (71%).
> Same issue causes MultiSource/Applications/lua/lua (46%).
> - SingleSource/Benchmarks/Misc/flops-2 (75%): Poor lowering of
> fneg:
> - FastISel:
> ldur d0, [x29,#-16]
> fneg d0, d0
> stur d0, [x29,#-16]
> - GlobalISel:
> ldur d0, [x29,#-64]
> orr x8, xzr, #0x8000000000000000
> fmov d1, x8
> fsub d0, d1, d0
> fmov x8, d0
> stur x8, [x29,#-64]
> - MultiSource/Benchmarks/Prolangs-C++/city/city...
2017 May 16
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...ating point data through an X register:
>>> >>
>>> >> FastISel:
>>> >> fadd d0, d1, d0
>>> >> str d0, [sp,#528]
>>> >> GlobalISel:
>>> >> fadd d0, d1, d0
>>> >> fmov x9, d0
>>> >> stur x9, [x29,#-48]
>>> >>
>>> >>
>>> >> Good finding, I forgot to do stores in my previous fix. I’ll do them
>>> >> shortly.
>>> >>
>>> >>
>>> >> Should be fixed by r302679
>>> >>
>...
2017 May 18
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...ec/mpeg2decode (46%):
> Function
> Reference_IDCT: Probably due to creating all constants in the entry BB
> +
> spilling floating point data through an X register:
>
> FastISel:
> fadd d0, d1, d0
> str d0, [sp,#528]
> GlobalISel:
> fadd d0, d1, d0
> fmov x9, d0
> stur x9, [x29,#-48]
>
>
> Good finding, I forgot to do stores in my previous fix. I’ll do them
> shortly.
>
>
> Should be fixed by r302679
>
>
> Thanks Quentin,
>
> That reduces the slow-down when enabling globalisel at -O0 from 13% (on
> r302453) to 9.5% (on r302...
2017 May 19
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...g all constants in the entry BB
>>> +
>>> spilling floating point data through an X register:
>>>
>>> FastISel:
>>> fadd d0, d1, d0
>>> str d0, [sp,#528]
>>> GlobalISel:
>>> fadd d0, d1, d0
>>> fmov x9, d0
>>> stur x9, [x29,#-48]
>>>
>>>
>>> Good finding, I forgot to do stores in my previous fix. I’ll do them
>>> shortly.
>>>
>>>
>>> Should be fixed by r302679
>>>
>>>
>>> Thanks Quentin,
>>>
>>> That re...
2017 May 22
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...ec/mpeg2decode (46%):
> Function
> Reference_IDCT: Probably due to creating all constants in the entry BB
> +
> spilling floating point data through an X register:
>
> FastISel:
> fadd d0, d1, d0
> str d0, [sp,#528]
> GlobalISel:
> fadd d0, d1, d0
> fmov x9, d0
> stur x9, [x29,#-48]
>
>
> Good finding, I forgot to do stores in my previous fix. I’ll do them
> shortly.
>
>
> Should be fixed by r302679
>
>
> Thanks Quentin,
>
> That reduces the slow-down when enabling globalisel at -O0 from 13% (on
> r302453) to 9.5% (on r302...
2017 Apr 27
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Kristof,
> On Apr 27, 2017, at 9:47 AM, Kristof Beyls <kristof.beyls at arm.com> wrote:
>
> Hi Quentin,
>
>> On 27 Apr 2017, at 00:48, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote:
>>
>> Hi Kristof,
>>
>>> On Apr 6, 2017, at 6:53 AM, Kristof Beyls <kristof.beyls at arm.com
2018 Jan 24
2
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
...unk/test/CodeGen/AArch64/arm64-memset-to-bzero.ll
> llvm/trunk/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
> llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
> llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
> llvm/trunk/test/CodeGen/AArch64/arm64-stur.ll
> llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll
> llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll
> llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
> llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll
> llvm/trunk/test/CodeGen/AArch64/ldst-pa...
2018 Jan 24
0
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
...-inline.ll
llvm/trunk/test/CodeGen/AArch64/arm64-memset-to-bzero.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
llvm/trunk/test/CodeGen/AArch64/arm64-stur.ll
llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll
llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll
llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll
llvm/trunk/test/CodeGen/AArch64/ldst-paired-aliasing.ll
llvm/t...
2018 Jan 25
2
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
.../AArch64/arm64-memset-to-bzero.ll
>> llvm/trunk/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
>> llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
>> llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
>> llvm/trunk/test/CodeGen/AArch64/arm64-stur.ll
>> llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll
>> llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll
>> llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
>> llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll
>> llvm/trunk/test/Cod...
2018 Jan 25
3
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
...emset-to-bzero.ll
>>> llvm/trunk/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
>>> llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
>>> llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
>>> llvm/trunk/test/CodeGen/AArch64/arm64-stur.ll
>>> llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll
>>> llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll
>>> llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
>>> llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll
>>>...
2018 Jan 25
0
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
...-inline.ll
llvm/trunk/test/CodeGen/AArch64/arm64-memset-to-bzero.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
llvm/trunk/test/CodeGen/AArch64/arm64-stur.ll
llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll
llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll
llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll
llvm/trunk/test/CodeGen/AArch64/ldst-paired-aliasing.ll
llvm/t...
2018 Jan 25
0
[PATCH] D41675: Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
...-inline.ll
llvm/trunk/test/CodeGen/AArch64/arm64-memset-to-bzero.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
llvm/trunk/test/CodeGen/AArch64/arm64-stur.ll
llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll
llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll
llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll
llvm/trunk/test/CodeGen/AArch64/ldst-paired-aliasing.ll
llvm/t...