Displaying 5 results from an estimated 5 matches for "strwui".
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strdup
2017 Oct 25
3
How vregs are assigned to operands in IR
...@printf(i8* getelementptr inbounds ([18
x i8], [18 x i8]* @.str, i32 0, i32 0), i32 %2)
ret i32 0
}
Generated machine instructions (initial)
BB#0: derived from LLVM BB %entry
%vreg11<def> = MOVi32imm 6; GPR32:%vreg11
%vreg12<def> = MOVi32imm 5; GPR32:%vreg12
STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
STRWui %vreg12, <fi#1>, 0; mem:ST4[FixedStack1] GPR32:%vreg12
STRWui %vreg11, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg11
.................................
Best
Nisal
2014 Apr 15
2
[LLVMdev] Proposal: AArch64/ARM64 merge from EuroLLVM
Hi Jiangning,
On Apr 14, 2014, at 10:31 PM, Jiangning Liu <liujiangning1 at gmail.com> wrote:
> Hi Jim,
>
> 2014-04-15 4:28 GMT+08:00 Jim Grosbach <grosbach at apple.com>:
> This sounds reasonable. Thanks, all.
>
> > - CSE of ADRP optimization (Jiangning)
>
> Quentin may have some input here. He’s done quite a lot of optimizations for ADRP sequences.
2014 Apr 16
3
[LLVMdev] Proposal: AArch64/ARM64 merge from EuroLLVM
...> %vreg5<def> = ADDxxi_lsl0_s %vreg4, <ga:@_MergedGlobals_x>[TF=11]; GPR64noxzr:%vreg5,%vreg4
> LS32_STR %vreg2, %vreg5<kill>, 1
>
> ARM64:
>
> %vreg2<def> = ADRP <ga:@_MergedGlobals_x>[TF=1]; GPR64common:%vreg2
> STRWui %vreg0, %vreg2<kill>, <ga:@_MergedGlobals_x>[TF=18]
> %vreg3<def> = MOVaddr <ga:@_MergedGlobals_x>[TF=1], <ga:@_MergedGlobals_x>[TF=18]; GPR64common:%vreg3
> STRWui %vreg1, %vreg3<kill>, 1
>
> The problem is MOVaddr generated for ARM6...
2018 Dec 05
2
Strange regalloc behaviour: one more available register causes much worse allocation
...2 = COPY %422:gpr32
7384B %419:gpr32 = COPY %417:gpr32
7392B %414:gpr32 = COPY %412:gpr32
7400B %409:gpr32 = COPY %407:gpr32
7408B %404:gpr32 = COPY %402:gpr32
7416B %399:gpr64 = COPY %397:gpr64
7424B %394:gpr32 = COPY %392:gpr32
7528B %253:gpr32 = MOVi32imm 28
7536B STRWui %253:gpr32, %182:gpr64common, 2 :: (store 4 into %ir.106, align 8)
7752B %392:gpr32 = COPY %394:gpr32
7756B %397:gpr64 = COPY %399:gpr64
7764B %402:gpr32 = COPY %404:gpr32
7768B %407:gpr32 = COPY %409:gpr32
7776B %412:gpr32 = COPY %414:gpr32
7780B %417:gpr32 = COPY %419:gpr3...
2018 Dec 05
3
Strange regalloc behaviour: one more available register causes much worse allocation
...2 = COPY %422:gpr32
7384B %419:gpr32 = COPY %417:gpr32
7392B %414:gpr32 = COPY %412:gpr32
7400B %409:gpr32 = COPY %407:gpr32
7408B %404:gpr32 = COPY %402:gpr32
7416B %399:gpr64 = COPY %397:gpr64
7424B %394:gpr32 = COPY %392:gpr32
7528B %253:gpr32 = MOVi32imm 28
7536B STRWui %253:gpr32, %182:gpr64common, 2 :: (store 4 into %ir.106, align 8)
7752B %392:gpr32 = COPY %394:gpr32
7756B %397:gpr64 = COPY %399:gpr64
7764B %402:gpr32 = COPY %404:gpr32
7768B %407:gpr32 = COPY %409:gpr32
7776B %412:gpr32 = COPY %414:gpr32
7780B %417:gpr32 = COPY %419:gpr3...