search for: strncasecmpz

...stringify(CONFIG_NOUVEAU_DEBUG_DEFAULT) ")"); +static int nouveau_debug_level = CONFIG_NOUVEAU_DEBUG_DEFAULT; +module_param_named(debug_level, nouveau_debug_level, int, 0400); + /* compares unterminated string 'str' with zero-terminated string 'cmp' */ static inline int strncasecmpz(const char *str, const char *cmp, size_t len) @@ -86,7 +93,7 @@ nouveau_boolopt(const char *optstr, const char *opt, bool value) int nouveau_dbgopt(const char *optstr, const char *sub) { - int mode = 1, level = CONFIG_NOUVEAU_DEBUG_DEFAULT; + int mode = 1, level = nouveau_debug_level; while...

some chipset have working engine reclocking, but broken memory reclocking like Fermi. We should for now, add the functionality to allow partly reclocking for those. Allthough this doesn't give as much performance as one might wish, it is till noticeable and may improve performance enough to be noted. Karol Herbst (2): clk: seperate engine and memory reclock toggles clk: allow engine

...t; - return -EINVAL; > - req = i; > - } > - > - return req + 2; > -} > - > static int > nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) > { > + struct nvkm_pstate *pstate; > int ret = 1; > > if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen)) > @@ -528,27 +507,46 @@ nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) > > ((char *)mode)[arglen] = '\0'; > if (!kstrtol(mode, 0, &v)) { > - ret = nvkm_clk_ustate_update(clk, v); > + ret = v; > if...

...= req) - break; - i++; - } - - if (pstate->pstate != req) - return -EINVAL; - req = i; - } - - return req + 2; -} - -static int nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) { + struct nvkm_pstate *pstate; int ret = 1; if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen)) @@ -528,27 +507,46 @@ nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) ((char *)mode)[arglen] = '\0'; if (!kstrtol(mode, 0, &v)) { - ret = nvkm_clk_ustate_update(clk, v); + ret = v; if (ret < 0) ret = 1; }...

...= req) - break; - i++; - } - - if (pstate->pstate != req) - return -EINVAL; - req = i; - } - - return req + 2; -} - static int nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) { + struct nvkm_pstate *pstate; int ret = 1; if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen)) @@ -528,27 +507,46 @@ nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) ((char *)mode)[arglen] = '\0'; if (!kstrtol(mode, 0, &v)) { - ret = nvkm_clk_ustate_update(clk, v); + ret = v; if (ret < 0) ret = 1; }...

There might be some callers of nouveau_clock_astate(), and they are from inetrrupt context. So we must ensure that this function can be atomic in that condition. This patch adds one parameter which is subsequently passed to nouveau_pstate_calc(). Therefore we can choose whether we want to wait for the pstate work's completion or not. Signed-off-by: Vince Hsu <vinceh at nvidia.com> ---

...uct nouveau_object *parent, ret = nouveau_pstate_new(clk, idx++); } while (ret == 0); + clk->allow_reclock = + nouveau_boolopt(device->cfgopt, "NvReclock", allow_reclock); + mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen); if (mode) { if (!strncasecmpz(mode, "disabled", arglen)) { diff --git a/nvkm/subdev/clock/nv04.c b/nvkm/subdev/clock/nv04.c index b74db6c..eb2d442 100644 --- a/nvkm/subdev/clock/nv04.c +++ b/nvkm/subdev/clock/nv04.c @@ -82,7 +82,8 @@ nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struc...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Hope I understood you correctly wrt the mem exec stuff. nvkm/subdev/fb/ramnv50.c | 2 +- nvkm/subdev/fb/ramnva3.c | 2 +- nvkm/subdev/fb/ramnvc0.c | 2 +- nvkm/subdev/fb/ramnve0.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/nvkm/subdev/fb/ramnv50.c b/nvkm/subdev/fb/ramnv50.c index ef91b6e..e5d12c2 100644

...e (ret == 0); > > + clk->allow_reclock = > + nouveau_boolopt(device->cfgopt, "NvReclock", allow_reclock); > + > mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen); > if (mode) { > if (!strncasecmpz(mode, "disabled", arglen)) { > diff --git a/nvkm/subdev/clock/nv04.c b/nvkm/subdev/clock/nv04.c > index b74db6c..eb2d442 100644 > --- a/nvkm/subdev/clock/nv04.c > +++ b/nvkm/subdev/clock/nv04.c > @@ -82,7 +82,8 @@ nv04_clock_ctor(struct nouveau_object *parent, struct nouvea...

Hi, This is a try to have some simple DVFS (Dynamic Voltage and Frequency Scaling) support for GK20A. Instead of relying on other existing frequency scaling framework, we create a simple subdev in Nouveau for the same purpose. That's because we don't want to make the DVFS implementation for GK20A far more than enough in the beginning and hinder the implementation for dGPU in the future.

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of changing the clock state due to temperature changes and dynamic reclocking. v2: remove commits

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended 3. racy reclocking while GPU is suspending and leading to hangs Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of changing the clock state due to

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended 3. nouveau always does full reclocks even if only a change of the voltage is required Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of

Adds Nouveau controlled thermal throttling for Kepler+ GPUs. With this I feel safe enough to add support for Maxwell2 reclocking later on (still hidden behind a switch, but we can be fairly sure to not overheat hardware if a user isn't carefull enough) Contains all patches from my clk update series, but I thought it makes sense to include those in this series as well for completness. Please

Just wanted to post updated versions of my last series/patches. Reviews welcomed. It would be also nice if we agree on features I should focus upstreaming, so that this work can be better splitted or reordered. Sadly most of my patches depend on the rather big clk subdev rework and I think those patches shows best, why I think this rework is actually needed and makes things much easier to add