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OK, thanks to the help of another forum user, I got my app compiled and working, but I now need to precache the OGG to memory. My current method somehow winds up in a loop or freezes the application. Here is y source for the decode/precache function. Why is it just freezing? I've let it run for about three minutes, thinking it was doing some heavy decoding, but I was wrong. Once this is

OK, I've been developing a small class that I can use in virtually any application to load and decode OGG files. Everything works fine until it reaches the line with the call to ov_open, then the application freezes and has to be killed. This is a single-threaded Win32 app. Below is both the structure that gets passed around, and my entire OGG class. Maybe one of you can figure this out.

Hello, from time to time I keep getting problems with some emails causing signal 6. I've already reported those, but it seems not to be easy to find the cause. From the logs, it seems to occur in sieve implementation. I've checked the email envelopes tody by accident, probably this part of my telnet session might help: a11 fetch 1 all * 1 FETCH (RFC822.SIZE 16750 INTERNALDATE

the files produced by windows compile vs. Linux are indeed significantly different in size (about 140K vs. 160) However I'm not convinced all the default parameters are set the same way in the two example files. This needs to be verified to see if there really is a bug, or can the two versions produce byte-equal output streams? <p> ___ Dan Miller (++,) Founder, On2 Technologies

On 25/05/2020 12:06, Aki Tuomi wrote: >> On 25/05/2020 13:00 Peter Nabbefeld <peter.nabbefeld at gmx.de> wrote: >> >> >> Hello, >> >> from time to time I keep getting problems with some emails causing >> signal 6. I've already reported those, but it seems not to be easy to >> find the cause. From the logs, it seems to occur in sieve

> On 25/05/2020 13:00 Peter Nabbefeld <peter.nabbefeld at gmx.de> wrote: > > > Hello, > > from time to time I keep getting problems with some emails causing > signal 6. I've already reported those, but it seems not to be easy to > find the cause. From the logs, it seems to occur in sieve implementation. > > I've checked the email envelopes tody by

Hi Michael, On 11/27/18 5:53 PM, Michael S. Tsirkin wrote: > On Thu, Nov 22, 2018 at 07:37:54PM +0000, Jean-Philippe Brucker wrote: >> Implement the virtio-iommu driver, following specification v0.9 [1]. >> >> Since v4 [2] I fixed the issues reported by Eric, and added Reviewed-by >> from Eric and Rob. Thanks! >> >> I changed the specification to fix one

Hi Michael, On 11/27/18 5:53 PM, Michael S. Tsirkin wrote: > On Thu, Nov 22, 2018 at 07:37:54PM +0000, Jean-Philippe Brucker wrote: >> Implement the virtio-iommu driver, following specification v0.9 [1]. >> >> Since v4 [2] I fixed the issues reported by Eric, and added Reviewed-by >> from Eric and Rob. Thanks! >> >> I changed the specification to fix one

I'm seeking feedback on multi-platform support for virtio-iommu. At the moment only devicetree (DT) is supported and we don't have a pleasant solution for other platforms. Once we figure out the topology description, x86 support is trivial. Since the IOMMU manages memory accesses from other devices, the guest kernel needs to initialize the IOMMU before endpoints start issuing DMA.

I'm seeking feedback on multi-platform support for virtio-iommu. At the moment only devicetree (DT) is supported and we don't have a pleasant solution for other platforms. Once we figure out the topology description, x86 support is trivial. Since the IOMMU manages memory accesses from other devices, the guest kernel needs to initialize the IOMMU before endpoints start issuing DMA.

Implement the virtio-iommu driver, following specification v0.8 [1]. Changes since v2 [2]: * Patches 2-4 allow virtio-iommu to use the PCI transport, since QEMU would like to phase out the MMIO transport. This produces a complex topology where the programming interface of the IOMMU could appear lower than the endpoints that it translates. It's not unheard of (e.g. AMD IOMMU), and the

Implement the virtio-iommu driver, following specification v0.8 [1]. Changes since v2 [2]: * Patches 2-4 allow virtio-iommu to use the PCI transport, since QEMU would like to phase out the MMIO transport. This produces a complex topology where the programming interface of the IOMMU could appear lower than the endpoints that it translates. It's not unheard of (e.g. AMD IOMMU), and the