search for: strconcat

...motivation behind Che-Liang's proposal. I do NOT want to factor out redundancy from instruction definitions like this: multiclass PTX_FLOAT_3OP<string opcstr> { def rr32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a, RegF32:$b), !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; def ri32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a, f32imm:$b), !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; def rr64 : InstPTX<(outs RegF64:$d), (in...

Is it legal to do something like a !strconcat on a non-string entity? That is, is there some operation that will let me do this (replace SOME_CONCAT with an appropriate operator): (WARNING! Hacked-up tablegen ahead!) multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, SDNode OpNo...

On Jun 15, 2009, at 11:33 AM, David Greene wrote: > To reduce redundancy, developers must be able to write generic > patterns > like this: > > [(set DSTREGCLASS:$dst, // rr, rrr > (xor (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src1))), > (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src2)))))], > > The substitution then fills in the appropriate types,

Chris Lattner wrote: > However, I don't see any reason to base this off of strings. Instead > of passing down "f32" as a string, why not do something like this > pseudo code: > > class X86ValueType { > RegisterClass RegClass; > ... > } > > def X86_f32 : X86ValueType { > let RegClass = FR32; > ... }; > def X86_i32 :

...We agree here. > I do NOT want to factor out redundancy from instruction definitions like this: > > multiclass PTX_FLOAT_3OP<string opcstr> { > def rr32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, RegF32:$b), > !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; > def ri32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, f32imm:$b), > !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; > def rr64 : InstPTX<(outs RegF64:$d), >...

...OpcodeString, string Intrinsic, string BaseType, list<list<dag>> ipatterns = [], string asm = "" > { def rr_Int : ... def rm_Int : ... def V#NAME#_128rrr_Int : fp_binary_vector_irrr< opc, // I'm not even sure this field reference will work !strconcat(OpcodeStr, !cast<X86ValueType>(!strconcat("X86v??", BaseType)).suffix, !strconcat(Intrinsic, !strconcat("_", !cast<X86ValueType>(!strconcat("X86v??&quot...

...pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, &...

On Mar 23, 2009, at 5:56 PM, David Greene wrote: > Is it legal to do something like a !strconcat on a non-string > entity? That > is, is there some operation that will let me do this (replace > SOME_CONCAT with > an appropriate operator): I don't get it, can you try a simpler example on me? :) -Chris > > > (WARNING! Hacked-up tablegen ahead!) > > multicl...

...; > In the absence of a much better proposal, I'd prefer to just keep it the way it is. Fair enough. What would make a better proposal? I'd like to keep the syntax concise. I wonder if there is a way we could get rid of the "operator" entirely and just specify names, like: strconcat("this", "that") instead of !strconcat("this", "that") What do you think? -Dave

...pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, &...

Evan Cheng <evan.cheng at apple.com> writes: > David, we cannot accept the 'multidef' keyword. Please revert it. Working on it now. > We appreciate you thinking ahead about MIC, but we are against the > massive refactoring and complicated abstraction scheme. We'll never > accept those patches. How about a less massive and complicated scheme? I think we can make

On Tuesday 24 March 2009 10:43, Chris Lattner wrote: > On Mar 23, 2009, at 5:56 PM, David Greene wrote: > > Is it legal to do something like a !strconcat on a non-string > > entity? That > > is, is there some operation that will let me do this (replace > > SOME_CONCAT with > > an appropriate operator): > > I don't get it, can you try a simpler example on me? :) Ok, let see if I can construct something. >From t...

...rn instruction for Cell SPU is "bi $lr". How do I jam that > into the instruction info w/o tblgen bitching up a storm about the > "$" or the extra "bi" operands? I am not sure. Does "bi \$lr" works? Or "bi $$lr"? Or even something like !strconcat("bi ", !strconcat("$", "lr")). > > - Immediates in a pattern: To move one register to another involves > using the 3-operand OR instruction, but how do I encode an immediate > w/o a type inference contradiction? > > def : Pat<(set R32C:$rDes...

...op, dag outs, dag ins, string asmstr, list<dag> pattern> > : Instruction { > let Namespace = "AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1...

...egen: ------------- Defs ----------------- def myImm5Class { // AsmOperandClass myAsmOperandClass string Name = "Class5"; } def myImm5 { // Operand AsmOperandClass ParserMatchClass = myImm5Class; } def anonymous_0 { // AsmOperandClass myAsmOperandClass string Name = !strconcat("Class", !cast<string>(myImmClass:n)); } def myImm6 { // Operand myImmClass AsmOperandClass ParserMatchClass = anonymous_0; } In the myImm5Class def used by myImm5, the !strconcat operation has been applied to compute the Name as "Class5". But in the anonymous def us...

..., 64], op_suffix = [r, i, r, i], op_type = [RegF32, f32imm, RegF64, f64imm], op_node_type = [RegF32, fpimm, RegF64, fpimm] in { def rr#op_suffix#nbit : InstPTX<(outs RegF#nbit:$d), (ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c), !strconcat(opcstr, ".f#nbit\t$d, $a, $b, $c"), [(set RegF#nbit:$d, (opnode2 (opnode1 RegF#nbit:$a, RegF#nbit:$b), #op_node_type:$c))]>; } } what if we instead did this: (Equivalent TableGen code with a for-loop) ------------------...

...multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> { > for nbit = [32, 32, 64, 64], > op_suffix = [r, i, r, i], > op_type = [RegF32, f32imm, RegF64, f64imm], > op_node_type = [RegF32, fpimm, RegF64, fpimm] in { > def !strconcat(!strconcat("rr", !cast<string>(op_suffix)), "nbit") > [...] > } > } > > Yes, it's a bit more verbose but also more flexible in what you can do > with iterator values. Here's some more detail on this. I want to be able to use #..# pasted...

I was able to resolve my previous question about dealing with custom loads/stores, and following Chris' suggestion, the IBM Cell SPU backend can generate code for "int main(void) { return 0; }" without crashing llc. There's a lot of work still to be done... like getting frame offsets correctly computed and hauling in the raft of intrinsics that the Cell SDK defines. Three quick

...en a complex example. Your second question is needs be answered first. null_frag causes the pattern to be dropped. Now having covered that the reason the operands are in the order they are is because the only instruction that doesn't use null_frag is this one defm r213 : fma3s_rm<opc213, !strconcat(OpStr, !strconcat("213", PackTy)), x86memop, RC, OpVT, mem_frag, OpNode> Which specifies the operand order as 213 thus why they are 2, 1, 3 in the pattern. ~Craig On Fri, Nov 16, 2012 at 12:19 AM, Anitha B Gollamudi < anitha.boyapati at gmail.com> wrote:...

...op, dag outs, dag ins, string asmstr, list<dag> pattern> > : Instruction { > let Namespace = "AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1...