search for: stratix

...The testbench uses the GHDL tool to simulate and can be download from the svn: http://svn.xiph.org/trunk/theora-fpga/idctslow/ Just run: $make $make run $make compare to see the testbench working and validating the module data output. This IDctSlow implementation was synthesized to the Altera Stratix II FPGA. The report is below: ------------------------------------ Analysis & Synthesis Status : Successful - Thu Jun 1 02:15:09 2006 Quartus II Version : 5.1 Build 176 10/26/2005 SJ Revision Name : idctslow Top-level Entity Name : IDctSlow Family : Stratix II Total combinational functions :...

Hi all, Just a stupid question The IDctSlow function on file idct.c has this line : ip[0] = (ogg_int16_t)((_Gd + _Cd ) >> 0); The ip[0] , _Gd and _Cd are of type ogg_int32_t My question is: The result of (_Gd + _Cd) can be a number with more than 16 bits ? (yes, it can be because they are int32, but the algorithm could guarantee something about that... I dont know...) If

...f Theora. 1 - Integration with a processor (Nios vs Leon) http://www.students.ic.unicamp.br/~ra031198/integration_processor.JPG We will need to compile the initial part of Theora in a processor and after to do a integration with the Hardware modules. For this, we will need to choose the processor. Stratix II (FPGA Altera) have a good support to NIOS. The alternative of a nonproprietary processor could be the LEON, but I think it maybe demand pretty much work to do run. 2 - To do a SDRAM controller. http://www.students.ic.unicamp.br/~ra031198/sdram_controller.JPG I think it is most important of all...

Hi people, As I said before: I did the IDCT to run on the FPGA. My friends from university did the Reconstruction routines running on the FPGA. I'm helping with the LoopFilter, and it is almost there. (all VHDL) I did a small profiling of the libTheora running on a Altera Stratix II device: The processor used was the NIOS II with 8Kb of data and instruction cache, branch prediction and hardware divider. (this is the more roubust NIOS II version). I decoded some frames of a 320x240 theora stream. Decoding all frames only in software (without the hardware modules) I got 44...

...Now I'm improving the latency of samples (number of clock cycles needed to decode a data sample). Report: -------------- Fitter Status : Successful - Mon Jun 5 16:38:21 2006 Quartus II Version : 5.1 Build 176 10/26/2005 SJ Revision Name : idctslow Top-level Entity Name : IDctSlow Family : Stratix II Device : EP2S60F672C5ES Timing Models : Final Total ALUTs : 2,538 / 48,352 ( 5 % ) Total registers : 466 Total pins : 54 / 493 ( 11 % ) Total virtual pins : 0 Total memory bits : 3,072 / 2,544,192 ( < 1 % ) DSP block 9-bit elements : 2 / 288 ( < 1 % ) Total PLLs : 0 / 6 ( 0 % ) Total DLLs...

...t is not show the name "Theora Hardware" because I am using a evaluation version of Grmon (the comunication interface with LEON3 on FPGA); You can also see the demostration using the LINUX: http://br.youtube.com/watch?v=NBLF6L5akJo This video shows the sequencie: - Programmer the board (Stratix II) with LEON3 (by USB Blaster - jtag); - Load the linux image on LEON3 (using grmon, by USB Blaster - jtag). - Open the kermit interface and set the configuration (by Serial Interface, in order to open a LINUX konsole that is runinng on FPGA); - Run the linux kernel (using grmon, by USB Blaster -...

...dded processor and to put just the critical modules in the hardware. Goal of my project is to give continuity to the project of the last year, putting one or more modules in hardware and then diminishing the cpu-time processing. This implementation will be done in VHDL and synthesized to the Altera Stratix II FPGA. Choosing the module I could cite now some of the functions of Theora to do this in hardware, but in order to choose a great module (or modules) to put it in hardware, I will study and do a good analysis in the begin of project as part of this. The functions that are interesting to be imp...