search for: stos

Hi I'm trying to get Dovecot to use Drupal users password for authenticating IMAP users. But I just cant figure out how to make Dovecot understand the password hash type that Drupal 7 is using. My example user with password Teacher1 looks like this in Drupal database: $S$DZwJa.U8HXT2PvTmwCK13rGEYEvnx5DB6/hlqnfCBum4s4U7MVWU Dovecot retrieves this hash but complains that its not a recognized

...Trace; c010b018 <common_interrupt+18/20> Trace; c010a0b8 <system_call+34/38> Trace; c010002b <startup_32+2b/11d> Code; c0142ba3 <ext3_new_block+557/6c8> 00000000 <_EIP>: Code; c0142ba3 <ext3_new_block+557/6c8> <===== 0: f3 ab repz stos %eax,%es:(%edi) <===== Code; c0142ba5 <ext3_new_block+559/6c8> 2: f6 c3 02 test $0x2,%bl Code; c0142ba8 <ext3_new_block+55c/6c8> 5: 74 02 je 9 <_EIP+0x9> c0142bac <ext3_new_block+560/6c8> Code; c0142baa <ext3_ne...

...void bar(int i) { 00000001400064E0 mov dword ptr [rsp+8],ecx 00000001400064E4 push rdi 00000001400064E5 sub rsp,20h 00000001400064E9 mov rdi,rsp 00000001400064EC mov rcx,8 00000001400064F6 mov eax,0CCCCCCCCh 00000001400064FB rep stos dword ptr [rdi] 00000001400064FD mov ecx,dword ptr [rsp+30h] printf("the int is %i\n",i); 0000000140006501 mov edx,dword ptr [i] 0000000140006505 lea rcx,[string "the int is %i\n" (140C1A240h)] 000000014000650C call qword ptr [_...

Memory mapped and port I/O is currently broken under VMX when the partition is running in VM8086 mode. The reason is that the instruction decoding support uses 32-bit opcode/address decodes rather 16-bit decodes. This patch fixes that. In addition, the patch adds support for the "stos" instruction decoding because this is a frequently used way to clear MMIO areas such as the screen. As an aside, vmx_platform.c should really reuse x86_emulate.c as much as possible. Signed-off-by: Leendert van Doorn <leendert@watson.ibm.com> ===== tools/ioemu/iodev/cpu.cc 1.7 vs edit...

...one line table > and one debug_info. Are you taking into account the relocation information? Use "objdump - Dr" on an the object file compiled by gcc -gdwarf-2, and you will see something like this (on x86-64): 0000000000000000 <.debug_info>: 0: aa stos %al,%es:(%rdi) 1: 00 00 add %al,(%rax) 3: 00 02 add %al,(%rdx) 5: 00 00 add %al,(%rax) 6: R_X86_64_32 .debug_abbrev 7: 00 00 add %al,(%rax) 9: 00 08...

...> 00000001400064E0 mov dword ptr [rsp+8],ecx > 00000001400064E4 push rdi > 00000001400064E5 sub rsp,20h > 00000001400064E9 mov rdi,rsp > 00000001400064EC mov rcx,8 > 00000001400064F6 mov eax,0CCCCCCCCh > 00000001400064FB rep stos dword ptr [rdi] > 00000001400064FD mov ecx,dword ptr [rsp+30h] > printf("the int is %i\n",i); > 0000000140006501 mov edx,dword ptr [i] > 0000000140006505 lea rcx,[string "the int is %i > \n" (140C1A240h)] > 000000014000650C c...

...Stack protection 002C13B0 push ebp 002C13B1 mov ebp,esp 002C13B3 sub esp,0C0h 002C13B9 push ebx 002C13BA push esi 002C13BB push edi 002C13BC lea edi,[ebp-0C0h] 002C13C2 mov ecx,30h 002C13C7 mov eax,0CCCCCCCCh 002C13CC rep stos dword ptr es:[edi] return mat->y; // Copy to address of first temporary variable. 002C13CE mov eax,dword ptr [mat] 002C13D1 add eax,10h 002C13D4 mov ecx,dword ptr [ebp+8] 002C13D7 mov edx,dword ptr [eax] 002C13D9 mov dword ptr [ecx],edx 00...

...copy) @@ -293,6 +293,9 @@ /// entry to the function and which must be maintained by every function. unsigned stackAlignment; + /// Whether function prologues should save register arguments on the stack. + bool SaveArgs; + /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops. /// unsigned MaxInlineSizeThreshold; @@ -356,6 +359,8 @@ return &getInstrInfo()->getRegisterInfo(); } + bool getSaveArgs() const { return SaveArgs; } + /// Returns the minimum alignment known to hold of the /// stack frame on entry to the function and which must b...

...x86/xen/xen-head.S @@ -28,14 +28,15 @@ ENTRY(startup_xen) /* Clear .bss */ xor %eax,%eax - mov $__bss_start, %_ASM_DI - mov $__bss_stop, %_ASM_CX + _ASM_MOVABS $__bss_start, %_ASM_DI + _ASM_MOVABS $__bss_stop, %_ASM_CX sub %_ASM_DI, %_ASM_CX shr $__ASM_SEL(2, 3), %_ASM_CX rep __ASM_SIZE(stos) - mov %_ASM_SI, xen_start_info - mov $init_thread_union+THREAD_SIZE, %_ASM_SP + _ASM_MOVABS $xen_start_info, %_ASM_AX + _ASM_MOV %_ASM_SI, (%_ASM_AX) + _ASM_MOVABS $init_thread_union+THREAD_SIZE, %_ASM_SP #ifdef CONFIG_X86_64 /* Set up %gs. @@ -46,7 +47,7 @@ ENTRY(startup_xen) * init dat...

...ads to void bar(int i) { 00000001400064E0 mov dword ptr [rsp+8],ecx 00000001400064E4 push rdi 00000001400064E5 sub rsp,20h 00000001400064E9 mov rdi,rsp 00000001400064EC mov rcx,8 00000001400064F6 mov eax,0CCCCCCCCh 00000001400064FB rep stos dword ptr [rdi] 00000001400064FD mov ecx,dword ptr [rsp+30h] printf("the int is %i\n",i); 0000000140006501 mov edx,dword ptr [i] 0000000140006505 lea rcx,[string "the int is %i\n" (140C1A240h)] 000000014000650C call qword ptr [__imp...

On 25 August 2010 18:54, Devang Patel <devang.patel at gmail.com> wrote: > See "DwarfDebug problem with line section" thread on llvmdev. Bottom line, > we may need a target specific patch for targets that do not follow dwarf > standard (as per my reading) in this particular case. Hi Devang, Ok, got the background, but will reply on this email. As far as I understood,

...o_target = mmio_inst.operand[1]; send_mmio_req(gpa, &mmio_inst, value, IOREQ_READ, 0); + return; } else { // Write to MMIO if (mmio_inst.operand[0] & IMMEDIATE) { @@ -728,6 +728,7 @@ if (!strncmp((char *)mmio_inst.i_name, "stos", 4)) { send_mmio_req(gpa, &mmio_inst, inst_decoder_regs->eax, IOREQ_WRITE, 0); + return; } domain_crash_synchronous(); diff -r febfcd0a1a0a -r 9a43d5c12b95 xen/arch/x86/vmx_intercept.c --- a/xen/arch/x86/vmx_intercept.c Thu Jun 30 03:20:48 2005...

...z, w; } float noise4(float4 v) { 0000000140067AE0 mov qword ptr [rsp+8],rcx 0000000140067AE5 push rdi 0000000140067AE6 sub rsp,10h 0000000140067AEA mov rdi,rsp 0000000140067AED mov rcx,4 0000000140067AF7 mov eax,0CCCCCCCCh 0000000140067AFC rep stos dword ptr [rdi] 0000000140067AFE mov rcx,qword ptr [rsp+20h] return v.x + v.y; 0000000140067B03 mov rax,qword ptr [v] 0000000140067B08 mov rcx,qword ptr [v] 0000000140067B0D movss xmm0,dword ptr [rax] 0000000140067B11 addss xmm0,dword ptr [rcx+4] 0000000...

See "DwarfDebug problem with line section" thread on llvmdev. Bottom line, we may need a target specific patch for targets that do not follow dwarf standard (as per my reading) in this particular case. - Devang On Wed, Aug 25, 2010 at 5:49 AM, Renato Golin <rengolin at systemcall.org>wrote: > Hi, > > I'm trying to compile two files together with debug information

...generates substantially better code than it used to and can take advantage of its powerful addressing modes. 23. Alkis wrote a generic "spiller" interface that can be used by arbitrary global register allocators. 24. The X86 code generator compiles memcpy and memset into rep movs/stos instructions. 25. Brian made the -print-machineinstrs debugging option common across all of the code generators. 26. Alkis converted the MachineBasicBlock class from "vector of pointers to instructions" to "doubly-linked ilist of instructions", making the code ge...

...generates substantially better code than it used to and can take advantage of its powerful addressing modes. 23. Alkis wrote a generic "spiller" interface that can be used by arbitrary global register allocators. 24. The X86 code generator compiles memcpy and memset into rep movs/stos instructions. 25. Brian made the -print-machineinstrs debugging option common across all of the code generators. 26. Alkis converted the MachineBasicBlock class from "vector of pointers to instructions" to "doubly-linked ilist of instructions", making the code ge...

...encodes a fixed constant address in the instruction without modrm byte. Basically opcodes 0xA0-0xA3 RawFrmSrc - Instruction uses SI/ESI/RSI as a source memory address. LODS and OUTS. RawFrmDst - Instruction uses DI/EDI/RDI as a destinatino memory address. Input in AL/AX/EAX/RAX for SCAS/STOS. Or DX for INS. RawFrmDstSrc - Instruction uses SI/ESI/RSI as a source memory address and DI/EDI/RDI as a destination memory address. MOVS and CMPS instructions. RawFrmImm8 - Rare instruction that has two immediates. The first is 8-bits the second one is controlled by ImmT field. RawFrmImm...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

...intas de él o los destinatarios. Cualquier opinión emitida en este correo electrónico es propia del autor o remitente y no representa necesariamente la opinión de la Caja Trujillo. A pesar de esfuerzos razonables en el control de virus y programas maliciosos, la Caja Trujillo no puede asegurar que éstos no se encuentren en este correo por causas ajenas a su control, por lo que usted debe analizar este correo y sus archivos adjuntos antes de abrirlos. Caja Municipal de Ahorro y Crédito de Trujillo www.cajatrujillo.com.pe " [[alternative HTML version deleted]]

Changes: - patch v2: - Adapt patch to work post KPTI and compiler changes - Redo all performance testing with latest configs and compilers - Simplify mov macro on PIE (MOVABS now) - Reduce GOT footprint - patch v1: - Simplify ftrace implementation. - Use gcc mstack-protector-guard-reg=%gs with PIE when possible. - rfc v3: - Use --emit-relocs instead of -pie to reduce