Displaying 6 results from an estimated 6 matches for "storeresult".
2008 May 20
2
[LLVMdev] Making use of SSE intrinsics
...nd any information on how to use
them. I've tried digging through the LLVM-GCC code but it's just too complex
for me. I would be very grateful if someone could complete this code:
LoadInst *x = new LoadInst(ptr_x, "", false, basicBlock);
// y = rcpps(x) // FIXME
StoreInst *storeResult = new StoreInst(y, ptr_y, false, basicBlock);
Somewhat related to this, I'd also like to know how to 'reinterpret_cast'
values. It can be quite useful to sometimes interpret a vector of
floating-point values as a vector of integers (for instance to extract the
sign, exponent and/or...
2008 May 20
0
[LLVMdev] Making use of SSE intrinsics
On Tue, May 20, 2008 at 5:03 AM, Nicolas Capens <nicolas at capens.net> wrote:
> LoadInst *x = new LoadInst(ptr_x, "", false, basicBlock);
>
> // y = rcpps(x) // FIXME
> StoreInst *storeResult = new StoreInst(y, ptr_y, false, basicBlock);
Using an IRBuilder, something like the following (uncompiled, but it's
at least approximately right):
Value* x = Builder.CreateLoad(ptr_x);
Function* rcpps = Intrinsic::getDeclaration(Module, Intrinsic::x86_sse_rcp_ps);
Value* y = Builder.CreateCal...
2016 Jun 15
3
[Proposal][RFC] Strided Memory Access Vectorization
...x i32> %stride.load28, <4 x i32> <i32 0, i32 3, i32 4, i32 7>
How STORE is modeled:
Store with stride 3 (i.e. store to c [ 3 * i ])
%10 = getelementptr inbounds i32, i32* %c, i64 %.lhs
%11 = bitcast i32* %10 to <4 x i32>*
%interleaved.vec = shufflevector <4 x i32> %StoreResult, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 1>
call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec, <4 x i32>* %11, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
%12 = getelementptr i32, i32* %10, i64 6
%13 = bitc...
2016 Jun 18
2
[Proposal][RFC] Strided Memory Access Vectorization
...;4 x i32> <i32 0, i32 3, i32 4, i32 7>
>
> How STORE is modeled:
> Store with stride 3 (i.e. store to c [ 3 * i ])
> %10 = getelementptr inbounds i32, i32* %c, i64 %.lhs
> %11 = bitcast i32* %10 to <4 x i32>*
> %interleaved.vec = shufflevector <4 x i32> %StoreResult, <4 x i32>
> undef, <4 x
> i32> <i32 0, i32 undef, i32 undef, i32 1>
> call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec, <4 x
> i32>* %11, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
> %12 = getelementptr i32, i...
2016 Jun 30
0
[Proposal][RFC] Strided Memory Access Vectorization
..., i32 4, i32 7>
> >
> > How STORE is modeled:
> > Store with stride 3 (i.e. store to c [ 3 * i ])
> > %10 = getelementptr inbounds i32, i32* %c, i64 %.lhs
> > %11 = bitcast i32* %10 to <4 x i32>*
> > %interleaved.vec = shufflevector <4 x i32> %StoreResult, <4 x i32>
> > undef, <4 x
> > i32> <i32 0, i32 undef, i32 undef, i32 1>
> > call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec, <4 x
> > i32>* %11, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
> > %12...
2016 Jun 30
1
[Proposal][RFC] Strided Memory Access Vectorization
..., i32 4, i32 7>
> >
> > How STORE is modeled:
> > Store with stride 3 (i.e. store to c [ 3 * i ])
> > %10 = getelementptr inbounds i32, i32* %c, i64 %.lhs
> > %11 = bitcast i32* %10 to <4 x i32>*
> > %interleaved.vec = shufflevector <4 x i32> %StoreResult, <4 x i32>
> > undef, <4 x
> > i32> <i32 0, i32 undef, i32 undef, i32 1>
> > call void @llvm.masked.store.v4i32(<4 x i32> %interleaved.vec, <4
> > x
> > i32>* %11, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
>...