Displaying 4 results from an estimated 4 matches for "storebos".
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2019 Nov 22
2
Tablegen PAT limitation?
def STOREbos { // InstructionEncoding Instruction RPPInst RPPInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 1, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0,...
2019 Nov 21
2
Tablegen PAT limitation?
...bsp; [(OpNode (v1i16 $rs1), (add (v1i32 (bitconvert (i32 $rbase))), (shl (v1i32 (sext (v1i16 $roffset))), (v1i32 (build_vector (uimm2 $rshift))) )))]>;
STOREbos(rs1, rbase, roffset, rshift): (store ?:{ *:[v1i16] }:$rs1, (add:{} (bitconvert:{ *:[v1i32] } ?:{ *:[i32] }:$rbase), (shl:{} (sext:{ *:[v1i32] } ?:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (uimm2:{} ?:{}:$rshift)))))
Included from /home/nancy/work/llvm-project/llvm/lib/Target/RPP/RPP.td:...
2019 Nov 25
2
Tablegen PAT limitation?
...lt;595602881 at qq.com>
Sent: Thursday, November 21, 2019 7:59 PM
To: Krzysztof Parzyszek <kparzysz at quicinc.com>; llvm-dev <llvm-dev at lists.llvm.org>
Subject: [EXT] Re:RE: Re:RE: Re:RE: [llvm-dev] Tablegen PAT limitation?
def STOREbos { // InstructionEncoding Instruction RPPInst RPPInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 1, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0...
2019 Nov 20
4
Tablegen PAT limitation?
...v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedstore>><<P:Predicate_store>>
RESULT: (STOREbos v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
DAGIselMatcherGen.cpp: 559
Pattern.getSrcPattern()->dump();
// list<dag> Pattern = [(store v1i16:$rs1, (add (v1i32 (bitconvert i32:$rbase)), (shl (v1i32...