Displaying 3 results from an estimated 3 matches for "store_reg_imm".
2007 Jul 24
1
[LLVMdev] alias information on machine instructions
...[??], it looks like the IsFrameIndex isn't getting set for the first
> instruction there.
yes, this needs to be added for each target. for our target i've
modified the loadRegFromStackSlot and storeRegToStackSlot methods to add
information on the frame index:
BuildMI(MB, MBI, TII.get(STORE_REG_IMM)).addReg(framePointer)
.addFrameIndex(FrameIndex).addReg(SrcReg).addSVOp(FrameIndex);
> I'm curious why you added a new node kind, TargetSrcValue, instead of just
> using the existing SRCVALUE.
this is needed to ensure that the lowering pass does not rewrite them. i
don't kno...
2007 Jul 23
0
[LLVMdev] alias information on machine instructions
On Mon, Jul 23, 2007 at 02:19:38PM +0200, Florian Brandner wrote:
> hi,
>
> i know it took a while, but here is a patch that adds a list of source
> values to machine instructions.
Cool!
> i've testet all this for our backend only, which is not public. i do not
> know how much has to be done to integrate this with the other, e.g., the
> x86, targets. does any of the
2007 Jul 23
1
[LLVMdev] alias information on machine instructions
hi,
i know it took a while, but here is a patch that adds a list of source
values to machine instructions.
i modified the DAGISelEmiter to automatically catch regular
loads/stores. custom instructions and loads/stores rewritten by the
lowering pass are not automatically captured.
during the instruction selection a source value operand is added to the
DAG for patterns matching a load/store.