Displaying 1 result from an estimated 1 matches for "store_load_latency_test".
2012 Jun 12
2
[LLVMdev] Latency of true depency of store followed by aliased load in ScheduleDAGInstrs
...estion regarding the latency of the true dependency of a
store followed by an aliased load in ScheduleDAGInstrs. The latency
seems to depend on the store and load being volatile or not as can be
seen in the post-RA-sched debug output of the attached ARM example:
$ llc -O3 -debug-only=post-RA-sched store_load_latency_test.ll
...
SU(2): STRi12 %R2<kill>, %R0<kill>, 0, pred:14, pred:%noreg; mem:Volatile ST4[%p1](tbaa=!"int")
# preds left : 1
# succs left : 2
# rdefs left : 0
Latency : 1
Depth : 2
Height : 0
Predecessors:...