search for: stoklund

Displaying 20 results from an estimated 905 matches for "stoklund".

2012 Sep 19
3
[LLVMdev] InlineSpiller Questions
Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: > On Sep 19, 2012, at 10:49 AM, <dag at cray.com> wrote: > >> Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: >> >> So if there are multiple values between r2 and r3 (r2.1, r2.2, etc.) I >> would just follow th...
2012 Aug 14
0
[LLVMdev] [RFC] Hexagon insn table refactoring
...attach. Anyone feel free to jump in via the mailing-list. TIA -- Evandro Menezes Austin, TX emenezes at codeaurora.org Qualcomm Innovation Center, Inc is a member of the Code Aurora Forum -------------- next part -------------- An embedded message was scrubbed... From: Jakob Stoklund Olesen <stoklund at 2pi.dk> Subject: Re: [LLVMdev] [RFC] Hexagon insn table refactoring Date: Mon, 13 Aug 2012 11:47:47 -0700 Size: 3124 URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120814/95e73c2b/attachment.eml> -------------- next part -------------- An embedded messa...
2012 Sep 19
0
[LLVMdev] InlineSpiller Questions
On Sep 19, 2012, at 4:02 PM, dag at cray.com wrote: > Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: > >> On Sep 19, 2012, at 10:49 AM, <dag at cray.com> wrote: >> >>> Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: >>> >>> So if there are multiple values between r2 and r3 (r2.1, r2.2, etc.) I &gt...
2012 Sep 19
2
[LLVMdev] InlineSpiller Questions
Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: >> If we decide to spill r3, we call traceSiblingValue to find the original >> def (the load). After traceSiblingValue we have the load instruction to >> define r1 and the value number information for r3. We don't have the >>...
2012 Aug 28
4
[LLVMdev] TableGen backend support to express relations between instruction
...query from this table. Thanks, Jyotsna -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Jyotsna Verma Sent: Tuesday, August 21, 2012 12:42 PM To: 'Jakob Stoklund Olesen' Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] TableGen related question for the Hexagon backend Sounds good. I've started adding TableGen backend support to emit relationship table into a .inc file. Hoping to finish it soon. Thanks for all your help. -Jyotsna -- Qualcomm Inn...
2011 Oct 11
2
[LLVMdev] Enhancing TableGen
On Oct 11, 2011, at 1:33 PM, David A. Greene wrote: > Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: > >> How about: > > foreach x = [...] > > I could do > > foreach x in [...] > > but that requires another keyword. Do we care? The syntax should be consistent with let expressions, even if the meaning is completely d...
2011 Nov 16
2
[LLVMdev] Possible Remat Bug
Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: > On Nov 16, 2011, at 9:15 AM, David Greene wrote: > >> I'm working on some enhancements to rematerialization that I hope to >> contribute. > > What do you have in mind? Rematting more types of loads. >> /// getReMatImpl...
2013 Apr 25
1
[LLVMdev] [PATCH] Handle tied sub-operands in AsmMatcherEmitter
Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote on 25.04.2013 18:58:05: > On Apr 25, 2013, at 4:44 AM, Ulrich Weigand <Ulrich.Weigand at de.ibm.com> wrote: > > > Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote on 24.04.2013 23:47:54: > > > >> I would like to add one...
2013 Apr 25
2
[LLVMdev] [PATCH] Handle tied sub-operands in AsmMatcherEmitter
Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote on 24.04.2013 23:47:54: > I would like to add one more case here: Fixed register operands. > > Some instructions, like x86's MUL and DIV, take operands in fixed > registers. Currently, we handle that with COPY instructions to and > from th...
2013 Jun 12
3
[LLVMdev] RFC - Profile Guided Optimization in LLVM
On Wed, Jun 12, 2013 at 3:10 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > It predates the block frequency interface. It just needs to be hooked up, > patches welcome. It would also be nice to remove the floating point > computations from the spill placement code. Cool, if Diego doesn't beat me to it, I may send yo...
2012 Aug 06
2
[LLVMdev] Register Coalescer does not preserve TargetFlag
On Aug 6, 2012, at 11:16 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > The getNextOperandForReg() function isn't used anywhere, Should we remove it? -Jim
2012 Aug 31
0
[LLVMdev] TableGen backend support to express relations between instruction
...ks, Jyotsna -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Jyotsna Verma Sent: Tuesday, August 28, 2012 1:01 PM To: 'Jakob Stoklund Olesen' Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] TableGen backend support to express relations between instruction Hi Jakob, Here is the first draft of the patch to add TableGen backend support for the instruction mapping tables. Please take a look and let me know your suggestions. A...
2012 Aug 03
3
[LLVMdev] TableGen related question for the Hexagon backend
On Thu, Aug 2, 2012 at 5:23 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > The problem is, this isn't really any better than having a large switch statement. You just moved the table into the .td file. > > You should be taking advantage of the instruction multiclasses so you don't have to maintain a full table of...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Fri, 8 Jun 2012 08:49:32 -0700 Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote: > > > For example, sometimes LiveIntervals asserts with: > > register: > > %CTR8 > > clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: > >...
2012 Nov 27
2
[LLVMdev] Move TargetRegisterInfo and TargetInstrInfo into libCodeGen
On Nov 27, 2012, at 11:23 AM, Chris Lattner <clattner at apple.com> wrote: > On Nov 27, 2012, at 10:24 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >> Would anyone object to my moving the TargetRegisterInfo and TargetInstrInfo classes into libCodeGen? >> >> TargetInstrInfo is already halfway there with its TargetInstrInfoImpl class implementing most shared functionality. The lib/Targe...
2013 Apr 06
3
[LLVMdev] [PATCH] RegScavenger::scavengeRegister
----- Original Message ----- > From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk> > To: "Akira Hatanaka" <ahatanak at gmail.com> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, "Hal Finkel" <hfinkel at anl.gov> > Sent: Tuesday, March 26, 2013 12:40:44 PM > Subject:...
2013 Apr 06
0
[LLVMdev] [PATCH] RegScavenger::scavengeRegister
On Apr 6, 2013, at 12:42 AM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- >> From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk> >> To: "Akira Hatanaka" <ahatanak at gmail.com> >> Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, "Hal Finkel" <hfinkel at anl.gov> >> Sent: Tuesday, March 26, 2013 12:40:44 PM &g...
2011 Nov 16
0
[LLVMdev] Possible Remat Bug
On Nov 16, 2011, at 10:23 AM, David A. Greene wrote: > Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: >> You want LiveRangeEdit::allUsesAvailableAt() which performs the same >> check today. > > But not in 3.0, right? Yes, 3.0 defaults to RAGreedy which uses the new spilling framework. It is ignoring the -spiller=... command line option....
2012 Jan 19
2
[LLVMdev] Best way to interface with MSVC _ftol2 runtime function for fptoui?
2012/1/18 Jakob Stoklund Olesen <stoklund at 2pi.dk>: > This should work: > %1 = call i64 asm "call __ftol2", "=A,{st},~{dirflag},~{fpsr},~{flags},~{st}" (double %x) nounwind Thanks Jakob, the ~{st} constraint does the trick. It wasn't clear to me that "clobbers" means "p...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 8, 2012, at 9:02 AM, Hal Finkel <hfinkel at anl.gov> wrote: > On Fri, 8 Jun 2012 08:49:32 -0700 > Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >> When machine code is still in SSA form, there are restrictions on >> what can be done with physical registers, which by their nature can't >> be in SSA form. Lang and I have been trying to come up with some >> rules, but we ha...