search for: stlr

Displaying 7 results from an estimated 7 matches for "stlr".

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2014 Dec 09
2
[LLVMdev] dmb ishld in AArch64
Hi Tim, > That barrier should be treated the same as any other dmb by LLVM. What > I'm most confused about is why it's there in the first place. From > what I can tell, the rcu_assign_pointer function should map to a > native store-release operation (stlr). I guess it's because we disabled the integrated-asm, so it won't complain when compiling the kernel. > Also, isn't the reordering wrong just from a data-dependency point of > view? It looks like it moves the hlist_pprev_rcu(n) access before the > n->pprev assignment. Cou...
2014 Dec 09
2
[LLVMdev] dmb ishld in AArch64
...er at gmail.com> wrote: > >> I guess it's because we disabled the integrated-asm, so it won't complain when compiling the kernel. > > No, it's something different. The inline assembly (for whatever > reason) says to use a "dmb ishst" rather than an "stlr". I don't > actually think the reason is that important, it's just surprising > because I'd expect stlr to be more efficient. I see .... guess I'm using an old version of Linux kernel ... from the Android branch ... > Thanks for the IR snippet (I agree, it does look...
2020 Jan 26
1
Timer doesn't appear to start
...can not get upssched.conf to work. On the old OS when I pull the power I would see a message in the syslog that a timer was set. On the new system I never see that message. I do get these new messages when I unplug the UPS to test Jan 26 16:51:27 nutpi upscode2[453]: Unknown response to UPDS: DI STLR Jan 26 16:51:27 nutpi upscode2[453]: Unknown response to UPDS: NO STOK Jan 26 16:51:27 nutpi upscode2[453]: Unknown response to UPDS: 11 STBO Jan 26 16:51:27 nutpi upscode2[453]: Unknown response to UPDS: 11 STBL Jan 26 16:51:27 nutpi upscode2[453]: Unknown response to UPDS: 00 STBM Jan 26 16:51:27...
2014 Dec 09
4
[LLVMdev] dmb ishld in AArch64
Hi, I got an optimization problem (O1, O2) regarding memory barrier “dmb ishld” I find in the test/CodeGen/AArch64/intrinsics-memory-barrier.ll , it’s stated that memory access around DMB should not be reordered, but when compiling the Linux kernel, I found load/store in static inline void hlist_add_before_rcu(struct hlist_node *n, struct hlist_node *next) { n->pprev
2014 Dec 09
4
[LLVMdev] dmb ishld in AArch64
I'm not sure, I was never able to compile the whole kernel with -O0, too many errors. Plus, the problem seems to be within machine code generation. I tried opt -O1 and -O2, the generated .ll file does not diff much for the target function (insert_leaf_info). Thanks, Chengyu > On Dec 9, 2014, at 4:49 PM, Tim Northover <t.p.northover at gmail.com> wrote: > > On 9 December 2014
2013 Jan 23
132
[PATCH 00/45] initial arm v8 (64-bit) support
First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I
2013 Feb 22
48
[PATCH v3 00/46] initial arm v8 (64-bit) support
This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.