Displaying 4 results from an estimated 4 matches for "stinst".
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s_inst
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...gt; bits<5> rt;
>> @@ -68,7 +93,24 @@ class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
>> // ST Instruction Class in V4 can take SLOT0& SLOT1.
>> // Definition of the instruction class CHANGED from V2/V3 to V4.
>> class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
>> - : InstHexagon<outs, ins, asmstr, pattern, "", ST> {
>> + : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
>> + bits<5> rd;
>> + bits<5> rs;...
2013 Apr 12
1
[LLVMdev] Problem with Store of i8 in a global address
...SDTCisPtrTy<0>]>;
def myCONST32 : SDNode<"myISD::CONST32", SDTmyCONST32>;
def myCONST32_GP : SDNode<"myISD::CONST32_GP", SDTmyCONST32>;
let PrintMethod = "printDMemOperand" in
def globaladdress : Operand<i32>;
def STdb : STInst<(outs),
(ins globaladdress:$addr, GPR32:$ra),
"stdb\t$addr, $ra",
[],
IIStore>
{
let mayStore = 1;
}
def : Pat<(atomic_store_8 (IcyflexCONST32_GP tglobal...
2008 Mar 12
3
[LLVMdev] Question about use-def chain
Programmers’ manual says we can iterate over a use-def chain by
op_iterator.
It works fine except for load and store instruction of stack variables.
For example, a simple bitcode is like the below.
i = alloca i32
store i32 0, i32* %i, align 4
%tmp1 = load i32* %i, align 4
If I apply a use-def chain to load instruction, I get alloca instruction.
I think store instruction is a correct
2005 Oct 16
2
[LLVMdev] Help on LLVM Instrumentation
Hi ,
I am using LLVM for my Post Graduate course project on Optimization. I am trying to do some insrtumentation to the bytecode.I 've been going through your Instrumentation code for the past few days in /llvm/lib/Transforms/Instrumentation folder and finally found two ways of instrumentation :
1) injecting LLVM bytecode instructions
2) calling an external C function.
I am trying both and