Displaying 5 results from an estimated 5 matches for "stfsx".
2011 Dec 20
2
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
...know how long the pipeline hazard will last.
It looks like this may have something to do with the height. Can you
explain how that is supposed to work?
For the specific example: We start with the initial store...
GPRC: 4 / 31
F4RC: 1 / 31
Examining Available:
Height 2: SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910,
0x2c03870, 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")>
[ORD=94] [ID=102]
Height 2: SU(97): 0x2c03470: ch = STFSX 0x2c03170, 0x2bf3910, 0x2c02c60,
0x2c03370<Mem:ST4[%arrayidx6.13](tbaa=!"float")> [ORD=88] [ID=97]
Height 2: SU(92):...
2011 Dec 20
0
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
...; It looks like this may have something to do with the height. Can you
> explain how that is supposed to work?
>
> For the specific example: We start with the initial store...
>
> GPRC: 4 / 31
> F4RC: 1 / 31
>
> Examining Available:
> Height 2: SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910,
> 0x2c03870, 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")>
> [ORD=94] [ID=102]
>
> Height 2: SU(97): 0x2c03470: ch = STFSX 0x2c03170, 0x2bf3910, 0x2c02c60,
> 0x2c03370<Mem:ST4[%arrayidx6.13](tbaa=!"float")> [ORD=88] [...
2011 Dec 20
1
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
...ing to do with the height. Can you
>> explain how that is supposed to work?
>>
>> For the specific example: We start with the initial store...
>>
>> GPRC: 4 / 31
>> F4RC: 1 / 31
>>
>> Examining Available:
>> Height 2: SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910,
>> 0x2c03870, 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")>
>> [ORD=94] [ID=102]
>>
>> Height 2: SU(97): 0x2c03470: ch = STFSX 0x2c03170, 0x2bf3910, 0x2c02c60,
>> 0x2c03370<Mem:ST4[%arrayidx6.13](tbaa=!"float&q...
2011 Dec 20
0
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote:
> Here's my "thought experiment" (from PR11589): I have a bunch of
> load-fadd-store chains to schedule. A store takes two cycles to clear
> its last pipeline stage. The fadd takes longer to compute its result
> (say 5 cycles), but can sustain a rate of 1 independent add per cycle.
> As the scheduling is bottom-up, it
2011 Dec 20
3
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
On Mon, 2011-12-19 at 22:14 -0800, Andrew Trick wrote:
> On Dec 19, 2011, at 3:19 PM, Hal Finkel wrote:
>
> > On Mon, 2011-12-19 at 07:41 -0800, Andrew Trick wrote:
> >> On Dec 19, 2011, at 6:51 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> >>
> >>> On Tue, 2011-10-25 at 21:00 -0700, Andrew Trick wrote:
> >>> Now, to generate the best