Displaying 12 results from an estimated 12 matches for "stfd".
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2012 May 02
4
[LLVMdev] [cfe-dev] Odd PPC inline asm constraint
...ack pointer and then uses small negative offsets (legal at this
point since we've already decremented the stack pointer) from that for
all of its saves/restores:
...
lis 0,0xffc7
mr 12,1
ori 0,0,7728
stwux 1,1,0
mflr 0
stw 0,4(12)
stfd 14,-144(12)
stfd 15,-136(12)
stfd 16,-128(12)
stfd 17,-120(12)
stfd 18,-112(12)
...
For things that don't work, do you have a small example program
that shows what's wrong?
Peter
2012 May 02
0
[LLVMdev] [cfe-dev] Odd PPC inline asm constraint
On Tue, 2012-05-01 at 17:47 -0500, Hal Finkel wrote:
> By default it should build for
> whatever the current host is (no special flags required). To
> specifically build for something else, use:
> -ccc-host-triple powerpc64-unknown-linux-gnu
> or
> -ccc-host-triple powerpc-unknown-linux-gnu
So LLVM isn't biarch capable? Meaning one LLVM compiler cannot
generate both
2012 May 12
0
[LLVMdev] [cfe-dev] Odd PPC inline asm constraint
...at this
> point since we've already decremented the stack pointer) from that for
> all of its saves/restores:
>
> ...
> lis 0,0xffc7
> mr 12,1
> ori 0,0,7728
> stwux 1,1,0
> mflr 0
> stw 0,4(12)
> stfd 14,-144(12)
> stfd 15,-136(12)
> stfd 16,-128(12)
> stfd 17,-120(12)
> stfd 18,-112(12)
> ...
> For things that don't work, do you have a small example program
> that shows what's wrong?
>
> Peter
>
>
>
>...
2012 May 01
4
[LLVMdev] [cfe-dev] Odd PPC inline asm constraint
On Tue, 01 May 2012 17:23:07 -0500
Peter Bergner <bergner at vnet.ibm.com> wrote:
> On Tue, 2012-05-01 at 16:06 -0500, Hal Finkel wrote:
> > LLVM/clang now will build in the normal way (./configure; make
> > install) on PPC (you'll need at least the 3.1 release candidate (or
> > trunk)). I generally build on my PPC64 hosts with:
> > make ENABLE_OPTIMIZED=1
2008 Jul 29
1
[LLVMdev] Vector types as function arguments and interfacing with C
...typedef double interval_t __attribute__ ((__vector_size__(16)));
interval_t add(interval_t a, interval_t b) {
return a + b;
}
to the following (under gcc version 4.0.1 (Apple Inc. build 5484))
_add:
lfd f0,80(r1)
lfd f12,64(r1)
lfd f13,72(r1)
fadd f12,f12,f0
lfd f0,88(r1)
fadd f13,f13,f0
stfd f12,-32(r1)
stfd f13,-24(r1)
lwz r3,-32(r1)
lwz r4,-28(r1)
lwz r5,-24(r1)
lwz r6,-20(r1)
blr
which means that GCC is choosing to pass the doubles on the stack
instead of in registers and so I cannot mix the LLVM code with the GCC
code.
Now, I realize that __vector_size__ is a GCC extens...
2008 Jul 29
0
[LLVMdev] Vector types as function arguments and interfacing with C
Hi,
> I want to be able to write a function like this
>
> define <2 x double> @add(<2 x double> %a, <2 x double> %b) nounwind {
> %c = add <2 x double> %a, %b
> ret <2 x double> %c
> }
>
> and then call it from C code. What is the appropriate translation of
> the <2 x double> vector type into C? I've tried packed structs
2008 Jul 29
2
[LLVMdev] Vector types as function arguments and interfacing with C
Hi,
I want to be able to write a function like this
define <2 x double> @add(<2 x double> %a, <2 x double> %b) nounwind {
%c = add <2 x double> %a, %b
ret <2 x double> %c
}
and then call it from C code. What is the appropriate translation of
the <2 x double> vector type into C? I've tried packed structs and
"typedef double vec_double
2006 May 15
1
[LLVMdev] Re: MRegisterInfo::storeRegToStackSlot question
Chris Lattner wrote:
> On Sat, 13 May 2006, Vladimir Prus wrote:
>> in LLVM CVS the afore-mentioned function has 'const TargetRegisterClass*'
>> parameter, that is not documented.
>>
>> Can somebody explain what does it mean?
>
> Basically, it gives the target more information about the spill. In
> particular, it specifies the register class to use
2011 Dec 14
0
[LLVMdev] Help with hazards
.....). For example, it will produce a schedule that looks
like...
SU(28): 0x127969b0: f64,ch = LFD 0x12793aa0, 0x1277b4f0,
0x127965b0<Mem:LD8[%scevgep100](tbaa=!"double")> [ORD=41] [ID=28]
SU(46): 0x12796ab0: f64 = FADD 0x127969b0, 0x127968b0 [ORD=42] [ID=46]
SU(27): 0x12796cb0: ch = STFD 0x12796ab0, 0x12793aa0, 0x1277b3f0,
0x127969b0:1<Mem:ST8[%scevgep103](tbaa=!"double")> [ORD=46] [ID=27]
SU(26): 0x127970b0: f64,ch = LFD 0x127941a0, 0x1277b4f0,
0x12796cb0<Mem:LD8[%scevgep94](align=16)(tbaa=!"double")> [ORD=50]
[ID=26]
SU(47): 0x127972c0: f64 = FADD...
2000 Nov 15
8
Optimisations
Looking through the archives I have seen talk of making CPU specific
optimisations for Vorbis, a la MMX/3DNow!/SSE. The feeling I gather is to
wait until something is working well in C before committing to any kind of
specific optimisation. What if oft used and needed DSP functions were
identified and standardised DSP functionality be written for Vorbis? This
would seperate the basically
2013 Aug 05
2
[LLVMdev] Many PPC64 failures with llvm 3.3
...] ******************** TEST 'LLVM :: CodeGen/PowerPC/2007-09-08-unaligned.ll' FAILED ********************
[ 1539s] Script:
[ 1539s] --
[ 1539s] /home/abuild/rpmbuild/BUILD/llvm-3.3/stage2/bin/./llc < /home/abuild/rpmbuild/BUILD/llvm-3.3/test/CodeGen/PowerPC/2007-09-08-unaligned.ll | grep stfd | /home/abuild/rpmbuild/BUILD/llvm-3.3/stage2/bin/./count 3
[ 1539s] /home/abuild/rpmbuild/BUILD/llvm-3.3/stage2/bin/./llc < /home/abuild/rpmbuild/BUILD/llvm-3.3/test/CodeGen/PowerPC/2007-09-08-unaligned.ll | grep stfs | /home/abuild/rpmbuild/BUILD/llvm-3.3/stage2/bin/./count 1
[ 1539s] /home/ab...
2013 Apr 18
0
Processed: adding new jessie tag to sid-tagged bugs
...s previously set
Ignoring request to alter tags of bug #395826 to the same tags previously set
> tags 667341 + jessie
Bug #667341 [gcc-4.7] gcc-4.7 can omit to list C++ templates as symbols
Added tag(s) jessie.
> tags 693633 + jessie
Bug #693633 [squeak-vm] squeak-vm: FTBFS on powerpcspe (asm stfd/lfd)
Added tag(s) jessie.
> tags 643208 + jessie
Bug #643208 [src:luakit] luakit: FTBFS: dpkg-buildpackage: error: dpkg-source -b luakit-2011.07.22-r1 gave error exit status 2
Added tag(s) jessie.
> tags 701257 + jessie
Bug #701257 [src:clam] clam: ftbfs with GCC-4.8
Added tag(s) jessie.
>...