Displaying 5 results from an estimated 5 matches for "stddw".
2011 Oct 27
0
[LLVMdev] Trunc Load
...for loading does not point
> to the address of the low word, but to the address of the high word.
This is contradictory: on a little-endian processor, the address for
loading a 64-bit value is same as the address of the low word. Are
you sure you're modeling the semantics of your lddw and stddw
instructions correctly?
-Eli
2011 Oct 27
2
[LLVMdev] Trunc Load
> Hi Johannes, what processor are you targeting? Is it little-endian or
> big-endian?
Little-endian. (The truth: you can set it manually, but it is set to
little endian, for sure.) The processor is a TI TMS320C64x.
Follow-up: I discovered that the "guilty" method is
DAGCombiner::ReduceLoadWidth. The error is introduced because the offset
is not calculated correctly.
The first
2011 Oct 27
2
[LLVMdev] Trunc Load
...load a singleword) gives an erroneous result. On my
architecture, this results in the high bits being loaded into the return
register, instead of the low bits, as should happen with truncate.
Details: i64 's are stored in two adjacent 32 bit registers. So the
store happens like this:
"stddw 0xBBBBBBBB33333333, *$ptr"
and the load should happen like this:
"lddw *$ptr, A5:A4"
. It is easy to see that if
"ldw *$ptr, A4"
is printed, then the high bits will be loaded into A4. Something like
this would be correct just like the lddw variant:
"ldw *-$ptr(4), A4&...
2011 Oct 27
0
[LLVMdev] Trunc Load
...an erroneous result. On my
> architecture, this results in the high bits being loaded into the return
> register, instead of the low bits, as should happen with truncate.
>
> Details: i64 's are stored in two adjacent 32 bit registers. So the
> store happens like this:
> "stddw 0xBBBBBBBB33333333, *$ptr"
> and the load should happen like this:
> "lddw *$ptr, A5:A4"
> . It is easy to see that if
> "ldw *$ptr, A4"
> is printed, then the high bits will be loaded into A4. Something like
> this would be correct just like the lddw vari...
2011 Oct 27
1
[LLVMdev] Trunc Load
> This is contradictory: on a little-endian processor, the address for
> loading a 64-bit value is same as the address of the low word. Are
> you sure you're modeling the semantics of your lddw and stddw
> instructions correctly?
... I thought so until now. Because I implemented stdw (store
doubleword) completely analogous to lddw: Just print out stdw with the
given pointer and the register pair, just like lddw. (This seems obvious.)
Well, ****. I just read the documentation very carefully (y...