Displaying 9 results from an estimated 9 matches for "statementreordering".
2013 Sep 25
0
[LLVMdev] [Polly] Performance comparison between Cloog and ISL code generation
...posted on http://188.40.87.11:8000/db_default/v4/nts/59?compare_to=58&baseline=58
It seems their execution-time performance are comparable:
Performance Regressions - Execution Time (ISL over Cloog)
MultiSource/Benchmarks/TSVC/ControlFlow-flt/ControlFlow-flt 8.49%
MultiSource/Benchmarks/TSVC/StatementReordering-flt/StatementReordering-flt 6.77%
MultiSource/Benchmarks/TSVC/CrossingThresholds-flt/CrossingThresholds-flt 2.65%
SingleSource/UnitTests/Vectorizer/gcc-loops 2.63%
Performance Improvements - Execution Time (ISL over Cloog)
MultiSource/Benchmarks/TSVC/NodeSplitting-flt/NodeSplitting-flt -6.77%
Mul...
2017 Jul 22
4
[RFC] Add IR level interprocedural outliner for code size.
...Early&Late Outlining", "Late Outlining" and "Machine
> Outliner"), with E&LO capturing most of the cases. Yet, they are very
> different:
>
> Test Suite, top improvements:
> E&LO:
>
> -
>
> enc-3des: 66.31%
> -
>
> StatementReordering-dbl: 51.45%
> -
>
> Symbolics-dbl: 51.42%
> -
>
> Recurrences-dbl: 51.38%
> -
>
> Packing-dbl: 51.33%
>
> LO:
>
> -
>
> enc-3des: 50.7%
> -
>
> ecbdes: 46.27%
> -
>
> security-rjindael:45.13%
>...
2015 Feb 26
5
[LLVMdev] [RFC] AArch64: Should we disable GlobalMerge?
Hi all,
I've started looking at the GlobalMerge pass, enabled by default on
ARM and AArch64. I think we should reconsider that, at least for
AArch64.
As is, the pass just merges all globals together, in groups of 4KB
(AArch64, 128B on ARM).
At the time it was enabled, the general thinking was "it's almost
free, it doesn't affect performance much, we might as well use it".
2018 Apr 26
0
Compare test-suite benchmarks performance complied without TBAA, with default TBAA and with new TBAA struct path
...01662|2.063396566| -0.05|17924201666| 0|2.063218715| -0.04|17924201666| 0|
|MultiSource/Benchmarks/TSVC/Searching-flt/Searching-flt.test | 40|2.057379471|17923778464|2.055515952| 0.09|17923778468| 0|2.055343632| 0.1|17923778467| 0|
|MultiSource/Benchmarks/TSVC/StatementReordering-dbl/StatementReordering-dbl.te| 40|2.267773304|15682563910|2.260157636| 0.34|15682563913| 0|2.268108021| -0.01|15682563915| 0|
|MultiSource/Benchmarks/TSVC/StatementReordering-flt/StatementReordering-flt.te| 40|1.580584254|15681328340|1.580687746| -0.01|15681328345| 0|1.579427267...
2015 May 15
6
[LLVMdev] Proposal: change LNT’s regression detection algorithm and how it is used to reduce false positives
tl;dr in low data situations we don’t look at past information, and that increases the false positive regression rate. We should look at the possibly incorrect recent past runs to fix that.
Motivation: LNT’s current regression detection system has false positive rate that is too high to make it useful. With test suites as large as the llvm “test-suite” a single report will show hundreds of
2015 May 18
2
[LLVMdev] Proposal: change LNT’s regression detection algorithm and how it is used to reduce false positives
...55.40s this program) nts.SingleSource/Benchmarks/Misc/ReedSolomon.exec
> 19. 43.27% cumulative (0.94% - 54.34s this program) nts.MultiSource/Benchmarks/TSVC/IndirectAddressing-flt/IndirectAddressing-flt.exec
> 20. 44.21% cumulative (0.94% - 54.20s this program) nts.MultiSource/Benchmarks/TSVC/StatementReordering-dbl/StatementReordering-dbl.exec
> 21. 45.12% cumulative (0.91% - 52.46s this program) nts.SingleSource/Benchmarks/Polybench/datamining/covariance/covariance.exec
> 22. 46.01% cumulative (0.89% - 51.49s this program) nts.MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk.exec
> 23. 46....
2017 Jul 20
8
[RFC] Add IR level interprocedural outliner for code size.
I’m River and I’m a compiler engineer at PlayStation. Recently, I’ve been
working on an interprocedural outlining (code folding) pass for code size
improvement at the IR level. We hit a couple of use cases that the current
code size solutions didn’t handle well enough. Outlining is one of the
avenues that seemed potentially beneficial.
-- Algorithmic Approach --
The general implementation can be
2013 Jul 28
0
[LLVMdev] IR Passes and TargetTransformInfo: Straw Man
...006 0.0
Benchmarks/Prolangs-C/simulator/simulator 0.0006 0.0006 0.0
Benchmarks/Prolangs-C/unix-tbl/unix-tbl 0.0006 0.0006 0.0
Benchmarks/TSVC/Recurrences-flt/Recurrences 2.7172 2.7173 0.00368025909023
Benchmarks/TSVC/StatementReordering-dbl/Sta 2.5547 2.555 0.01174306180765
Benchmarks/Trimaran/enc-md5/enc-md5 1.2119 1.2126 0.05776054129878
Benchmarks/MiBench/automotive-basicmath/aut 0.1698 0.1699 0.05889281507655
Benchmarks/ASC_Sequoia/IRSmk/IRSmk 2.6607 2.6626 0.071409...
2013 Jul 18
3
[LLVMdev] IR Passes and TargetTransformInfo: Straw Man
Andy and I briefly discussed this the other day, we have not yet got
chance to list a detailed pass order
for the pre- and post- IPO scalar optimizations.
This is wish-list in our mind:
pre-IPO: based on the ordering he propose, get rid of the inlining (or
just inline tiny func), get rid of
all loop xforms...
post-IPO: get rid of inlining, or maybe we still need it, only