search for: stackifying

On 7/26/05, Reid Spencer <reid at x10sys.com> wrote: > On Tue, 2005-07-26 at 17:25 -0700, Michael McCracken wrote: > > > Since I'm modifying llc, I have a couple small questions about that code: > > > > opt and analyze (and a couple of other places) add a verifier pass, > > but llc doesn't. > > This would seem to make sense for llc as well -

On Tue, 26 Jul 2005, Michael McCracken wrote: >> I can't see any harm in that. However, please make sure that it really >> isn't being run. The verifier can be hidden by various levels of >> abstraction. > > Assuming that I get everything with -debug-pass=Structure, then it isn't: -debug-pass=Structure does list everything. If you add it, please add it in an

Attached is my patch that adds a (debug build only) verifier pass and support for creating passes specified on the command line to llc. Let me know if it needs changes to be acceptable. One thing I noticed is that (eg.) opt and analyze have their options and globals in an anonymous namespace while llc doesn't. I just used llc's convention - which is preferable? As to testing - It works

Dear LLVM guys, I am getting an error with my pass implementation, and I cannot figure it out. Basically, I've implemented part of a register allocation algorithm, but I am having problems to set the passes correctly. For instance, for this program below, the following error message is produced: .c ----------------------| .bc ---------------------------------

On Fri, 23 Jun 2006, Fernando Magno Quintao Pereira wrote: > I am getting an error with my pass implementation, and I cannot figure > it out. Basically, I've implemented part of a register allocation > algorithm, but I am having problems to set the passes correctly. For > instance, for this program below, the following error message is > produced: It's hard to say

Hi all, we're looking around a bit for a small and simple stack-based architecture, that we could use as a sidekick to the DSP processor we are developing. We've been looking at ZPU for a bit, but are also considering developing our own hardware for this (possibly very much tuned to LLVM). Of course, that would also mean building an LLVM backend. I guess having a very simple backend

On Feb 22, 2009, at 5:43 PM, Wesley J. Landaker wrote: > > I would love to see a Kalescope-like tutorial that goes step-by-step > through > making a backend. At the very least, I'll be documenting my > adventure, so > maybe once I know what I'm doing I can turn it into a tutorial. Have you seen: http://llvm.org/docs/WritingAnLLVMBackend.html If you're targeting

In the X86RegisterInfo.td file, RST is defined like this: // Floating point stack registers (these are not allocatable by the // register allocator - the floating point stackifier is responsible // for transforming FPn allocations to STn registers) def RST : RegisterClass<"X86", [f64], 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { let MethodProtos =

Hi all, I was asked to write a C compiler back end for a dated stack based architecture, i.e. once whose instructions operate only on the top elements of a stack and doesn't use arguments, something like the JVM. I looked at some open source compilers (gcc, sdcc, tinyc and LLVM). To me LLVM seems promising (and I likes C++). Because I'm new here I need your help to understand if: 1)

Dear LLVM guys, I've solved my problem with the passes, and compiled my first code using the new register allocator! Debugging was quite easy, using gdb. The problem was that I was forgetting to initialize the array that records the physical registers ever used (MachineFunction::UsedPhysRegs). This is a very minor thing, but I would suggest asserting that the vector has been initialized

On Tue, 2005-07-26 at 17:25 -0700, Michael McCracken wrote: > Since I'm modifying llc, I have a couple small questions about that code: > > opt and analyze (and a couple of other places) add a verifier pass, > but llc doesn't. > This would seem to make sense for llc as well - should I add it, with > the corresponding > hidden -no-verify option? I can't see any

On Sunday 22 February 2009 23:18:25 Chris Lattner wrote: > Have you seen: > http://llvm.org/docs/WritingAnLLVMBackend.html I have, and it's certainly helpful. Since the Kalescope tutorial is so amazingly easy to work through that it makes me jealous for a similar tutorial on the backend. But I'm definitely not complaining. =) > If you're targeting a stack machine, I'd

On Sunday 22 February 2009 17:06:06 Eli Friedman wrote: > On Sun, Feb 22, 2009 at 3:25 PM, Wesley J. Landaker <wjl at icecavern.net> wrote: > > * Has anyone else out there targeted (or tried to target) a stack > > machine before? Was it successfull? What problems did you have? > > Haven't done that, and I don't think there are any existing backends > like

Hi, I have an ir at the end of this email. Run it with: llc -mcpu=i386 -march=x86-64 -mattr=-sse2 and get assertion below. Changing cpu does not help. I am using llc from the latest svn repository. Any suggestions to work around this? I need to disable sse2 instructions for x86-64. Thanks, -Peng -----error message------ llc: X86FloatingPoint.cpp:332: unsigned int getFPReg(const

On 7/25/05, Reid Spencer <reid at x10sys.com> wrote: > On Mon, 2005-07-25 at 21:48 -0700, Michael McCracken wrote: > > On 7/25/05, Reid Spencer <reid at x10sys.com> wrote: > > > Why not just create your pass as a shared object and: > > > > > > opt -load mypass.so -mypass | llc > > > > My pass is an implementation of an analysis group that

On Nov 19, 2009, at 5:28 PM, Jon Harrop wrote: > > Are these barfs due to bugs in my generated code or is this parts of LLVM not > honoring tail calls? It was a bug in LLVM, with emitting tail calls at -O0. It's now fixed, as of r89444. Dan

On Friday 20 November 2009 02:54:14 Dan Gohman wrote: > On Nov 19, 2009, at 5:28 PM, Jon Harrop wrote: > > Are these barfs due to bugs in my generated code or is this parts of LLVM > > not honoring tail calls? > > It was a bug in LLVM, with emitting tail calls at -O0. It's now > fixed, as of r89444. Awesome, thanks. What about this one where the simple register

Hi, I'm trying to have another stab at writing an LLVM ZPU backend. Any pointers or encouragement would be greatly appreciated. So far I've been wandering around the LLVM trying to read up and I've hacked together something that builds just to experiment and get a feel for the build system. I was able to write a backend for GCC which has been in use for years now, but I can't

Whoops! Forgot to CC: the list! ----- Forwarded Message ----- > From:Samuel Crow <samuraileumas at yahoo.com> > To:Øyvind Harboe <oyvind.harboe at zylin.com> > Cc: > Sent:Thursday, November 18, 2010 7:22:39 PM > Subject:Re: [LLVMdev] Writing a backend for the ZPU > > > Hello, Some > thoughts/problems: - In GCC I created > registers which were

On Tue, 19 Oct 2004, Zhang Qiuyu wrote: > I wrote a machinefunction pass to try to see what's going on. Does it > mean that it is target machine dependent pass, like x86? However, after > compile it, I found there wasnot command option I registered. I used > regular way to do it like RegisterOpt <...> X("... ", "... "), but I > cannot see the optimized